Michael Stockinger

Engineering single NMOS and PMOS output buffers for maximum failure voltage in advanced CMOS technologies

In this paper we propose new circuit design options for increasing the ldquoeffectiverdquo failure voltage (Vt2) of both NMOS and PMOS output buffer transistors, thereby helping to protect these fragile devices. Using experimental data, device and circuit simulations we demonstrate how placing a series resistor and either a bias circuit for the buffer gates or secondary ESD diodes may significantly increase Vt2.

Advanced ESD rail clamp network design for high voltage CMOS applications

We present a new boosted and distributed ESD rail clamp protection approach for high voltage CMOS applications using stacked active MOSFET rail clamps and provide design guidelines for practical pad ring scenarios. This approach offers improved ESD robustness, area compactness, layout modularity, process portability, scalability, and ease of simulation.

A novel testing approach for full-chip CDM characterization

This work describes a new testing system for use in measuring the full-chip response to CDM-like discharge phenomena. It includes a new form of the cc-TLP system and monitoring strategies that allow measurement of internal voltage waveforms during a discharge.

Unexpected Latch-Up Through CMOS Triple-Well Structures

Unexpected device interactions between ESD diodes and NMOS clamps in isolated P-well (triple well) have been observed. This can lead to an SCR-like I-V behavior in TLP measurements and poses a latch-up risk. The cause of this interaction is being analyzed using equivalent circuits with parasitic devices and by TCAD simulations.

RC triggered active ESD clamps; How should they behave under powered conditions?

Problems with standard RC clamp circuits during powered system level ESD events are reviewed. A new clamp design is presented which employs a proportional triggering scheme that regulates the pad voltage during transient events, rather than simply switching the clamps fully on or off.

A Shared Architecture for a Dynamic TechnologySimulation Repository

In this paper, the design of a shared technology simulation repository is described. This system allows the download, archival, and simultaneous translation of equipment recipe and run data into a shared, revision controlled repository, as well as the automated generation of Technology Computer Aided Design (TCAD) input. Based on this system Computer Integrated Manufacturing (CIM) data and integrated circuit layout data can be combined to provide rapid technology optimization, enabling new methods of technology development.