Fred Harris

Synchronization in software radios. Carrier and timing recovery using FPGAs

Software defined radios (SDR) are highly configurable hardware platforms that provide the technology for realizing the rapidly expanding third (and future) generation digital wireless communication infrastructure. Many sophisticated signal processing tasks are performed in a SDR, including advanced compression algorithms, power control, channel estimation, equalization, forward error control and protocol management. While there is a plethora of silicon alternatives available for implementing the various functions in a SDR, field programmable gate arrays (FPGAs) are an attractive option for many of these tasks for reasons of performance, power consumption and configurability. Amongst the more complex tasks performed in a high data rate wireless system is synchronization. This paper is about carrier and timing synchronization in SDRs using FPGA based signal processors. We describe and examine a QPSK Costas loop for performing coherent demodulation, and report on the implications of an FPGA mechanization. Symbol timing recovery is addressed using a differential matched filter control system. A tutorial style approach is adopted to describe the operation of the timing recovery loop and considerations for FPGA implementation are outlined.

Design of wideband CIC compensator filter for a digital IF receiver

This paper presents the multiplierless CIC compensation filter based on the 2M-order filter and the sharpening technique. This technique proposed by Kaiser and Hamming attempts to improve the pass band and the stop band of a symmetric nonrecursive filter using the multiple copies of the same filter. We have considered the simplest sharpening polynomial that improves the frequency characteristic with minimum increase in computational complexity. The proposed filter provides wideband compensation over the specified CIC main lobe bandwidth. The design parameter is a single integer b which depends on K, the number of cascade CIC stages and is independent on the decimation factor M. The values of b tabulated here were obtained from MATLAB simulations. A number of demonstrated characteristics make the proposed structure a good candidate for software defined radio (SDR) applications.

FPGA Implementation of Carrier Synchronization for QAM Receivers

Software defined radios (SDR) are highly configurable hardware platforms that provide the technology for realizing the rapidly expanding third (and future) generation digital wireless communication infrastructure. While there are a number of silicon alternatives available for implementing the various functions in a SDR, field programmable gate arrays (FPGAs) are an attractive option for many of these tasks for reasons of performance, power consumption and flexibility. Amongst the more complex tasks performed in a high data rate wireless system is synchronization. This paper examines carrier synchronization in SDRs using FPGA based signal processors. We provide a tutorial style overview of carrier recovery techniques for QPSK and QAM modulation schemes and report on the design and FPGA implementation of a carrier recovery loop for a 16-QAM modern. Two design alternatives are presented to highlight the rich design space accessible using configurable logic. The FPGA device utilization and performance for a carrier recovery circuit using a look-up table approach and CORDIC arithmetic are presented. The simulation and FPGA implementation process using a recent system level design tool called System Generator™ for DSP described.

An introduction to FFT and time domain windows

This paper includes a brief tutorial on digital spectrum analysis and FFT-related issues to form spectral estimates on digitized signals. Some review of the DFT has been presented, and some discussion on the computational advantages of the FFT calculation has also been presented. Finally, the main considerations on windowing and window characteristics have been briefly discussed.

Software defined radio: Part 22 in a series of tutorials on instrumentation and measurement

A software defined radio (SDR) is a communication system that performs many of its required signal processing tasks in a programmable digital signal processing (DSP) engine. The engine is coupled to the air interface of analog circuits and antennae by analog-to-digital and digital-to-analog converters (ADCs and DACs). The SDRs software reprograms the DSP segment of the radios physical layer to reconFigure the radio system parameters and can thus synthesize multiple radios. The software can also select and alter the air interface components as well as the higher level data processing layers of the radio system.

Real-Time QRD-Based Beamforming on an FPGA Platform

This paper describes the architecture, design flow and verification process for the FPGA implementation of a realtime beamformer. One of the challenges in realizing this class of processing is in the implementation of the linear algebra operations required in forming the least-squares solution to the Normal equations. We describe the FPGA realization of a flexible QRD-based approach to this problem in which the system parameters (row and column dimensions) can be supplied to the beamformer module at run-time. The design and FPGA implementation of the beamformer architecture and verification framework is described along with implementation considerations for Xilinx Virtextrade-4 family of FPGAs. A model-based FPGA design flow called System Generatortrade [4], based on the The Mathworks Simulinkregvisual programming environment, was used exclusively to generate the implementation. The use of this tool chain for hardware verification is discussed. The FPGA resource utilization and performance of the QRD processor is reported.

On design of two-stage CIC compensation filter

This paper presents the compensation filter design for the two-stage CIC decimation filter. The goal is twofold: to avoid the integrator section at high input rate and obtain a low wideband passband droop of the overall filter. To this end the decimation is split into two stages with the cascaded less order RRS filters at each stage. The first stage can be implemented either in non recursive form or using the polyphase decomposition. The simple compensation filter and the sharpening are applied to the second section where RRS filter is implemented as a CIC filter. The resulting structure is a multiplierless and with no integrators at high input rate. Additionally, the structure exhibits a low passband droop and a high stopband attenuation.

Fixed length FIR filters with continuously variable bandwidth

Software defined radios require filters of different bandwidths to process the many different bandwidth signals plucked from the ether. Filters with different fractional bandwidth, fBW/fSMPL, have different lengths or number of taps, that varies inversely with the fractional bandwidth. Different length filters require different computational resources which include data registers, multipliers, and filter coefficients. This paper describes a filter architecture that supports variable bandwidth FIR filters with fixed computational resources.

Design of CIC Compensator Filter in a Digital IF Receiver

This paper presents a simple multiplier less CIC compensation filter based on the sharpening technique. The proposed filter provides the narrowband compensation, as well as the wideband compensation in the band which is frac34 of the overall band after decimation. The design parameter is the integer b which depends on the number of the cascaded CIC filters. The values of b are given in the table obtained using different simulations in MATLAB.

Direct digital synthesis - some options for FPGA implementation

Direct digital synthesizers (DDS), or numerically controlled oscillators, are a functional requirement of virtually every digital communications system, including modems and software defined radios. Frequency synthesis is commonly realized using application specific standard parts or as software on a DSP processor. With ever increasing amounts of digital signal processing being realized using field programmable gate array (FPGA) based hardware platforms, it is fruitful to explore various DDS architectures and evaluate the many possible architecture/performance tradeoffs with a view to FPGA implementation. This paper describes three DDS architectures and presents several designs that illustrate DDS performance and highlight design considerations for FPGA implementation.