Christian Beckhoff

ReCoBus-Builder — A novel tool and technique to build statically and dynamically reconfigurable systems for FPGAS

In this paper, we present the ReCoBus-builder tool chain that simplifies the generation of dynamically reconfigurable systems to almost a push-button process. The generated systems provide one or more resource areas that will be used by different partially reconfigurable modules at runtime. It is possible to integrate multiple partially reconfigurable modules into the same resource area at the same time and these modules can communicate via a fixed bus infrastructure or dedicated point-to-point links with other parts of the system. This allows building encapsulated modules that will be integrated into the system by linking together bitstreams at runtime. We will demonstrate that bitstream linking can further be used to speed up the design process of static only systems by eliminating long synthesis runs or place and route steps, when only small portions of a design are exchanged.

Go Ahead: A Partial Reconfiguration Framework

Exploiting the benefits of partial run-time reconfiguration requires efficient tools. In this paper, we introduce the tool Go Ahead that is able to implement run-time reconfigurable systems for all recent Xilinx FPGAs. This includes in particular support for low cost and low power Spartan-6 FPGAs. Go Ahead assists during floor planning and automates the constraint generation. It interacts with the Xilinx vendor tools and triggers the physical implementation phases all the way down to the final configuration bit streams. Go Ahead enables the building of flexible systems for integrating many reconfigurable modules very efficiently into a system. The tool targets (re)usability, portability to future devices, and migration paths among reconfigurable systems featuring different FPGAs or even FPGA families. Moreover, it provides a scripting interface and all features can be accessed remotely.

The Xilinx Design Language (XDL): Tutorial and use cases

With the Xilinx Design Language (XDL), the FPGA vendor Xilinx offers a very powerful interface that provides access to virtually all features of their devices. This includes on one side the generation of complete device descriptions containing information about the FPGA primitives and the routing fabric. On the other side, XDL can be used to constrain systems or to directly implement modules or macros for Xilinx FPGAs. In this paper, we will provide documentation on the language and reveal several use cases for this language.

Bitstream Decompression for High Speed FPGA Configuration from Slow Memories

In this paper, we present hardware decompression accelerators for bridging the gap between high speed FPGA configuration interfaces and slow configuration memories. We discuss different compression algorithms suitable for a decompression on FPGAs as well as on CPLDs with respect to the achievable compression ratio, throughput, and hardware overhead. This leads to various decompressor implementations with one capable to decompress at high data rates of up to 400 megabytes per second while only requiring slightly more than a hundred look-up tables. Furthermore, we present a sophisticated configuration bitstream benchmark.

A communication architecture for complex runtime reconfigurable systems and its implementation on spartan-3 FPGAs

In this paper, we present and analyze a sophisticated communication architecture that allows to integrate many different modules into a system by FPGA reconfiguration at runtime. Furthermore, we examine how this architecture can be implemented on low-cost Spartan-3 devices. It will be demonstrated that modules can be exchanged in a system without disturbing the communication architecture. The paper points out, that the capabilities of Spartan-3 FPGAs are sufficient to build complex reconfigurable systems.

Short-Circuits on FPGAs Caused by Partial Runtime Reconfiguration

In this paper, we show how short-circuits on FPGAs can be caused by partial runtime reconfiguration. Short-circuit can even occur on FPGAs that do not offer any tristate resources just by using off the shelf vendor tools without any bitstream manipulation. The duration of the here presented short-circuits ranges from short spikes up to persistent short-circuits that remain active during runtime. Short-circuits will result in increased current consumption and can thus harm the system and must therefore be prevented. An algorithm is derived that detects whether configuration data will cause short-circuits. We implemented this algorithm in a bitstream scanner that can also be used in systems at runtime.

Hardware Decompression Techniques for FPGA-Based Embedded Systems

In this work, we present hardware decompression accelerators for widening the bottleneck between slow nonvolatile memories on the one side and high-speed FPGA configuration interfaces and fast softcore CPUs on the other side. We discuss different compression algorithms suitable for a hardware accelerated decompression on FPGAs as well as on CPLDs. The algorithms will be investigated with respect to the achievable compression ratio, throughput, and hardware overhead. This leads to various decompressor implementations with one capable to decompress at high data rates of up to 400 megabytes per second under optimal conditions while only requiring slightly more than a hundred lookup tables. We will evaluate how these decompressors perform on configuration bitstreams for different FPGAs as well as for softcore CPU binaries.

Minimizing Internal Fragmentation by Fine-Grained Two-Dimensional Module Placement for Runtime Reconfiguralble Systems

This paper analyzes fragmentation issues and proves that the reconfigurable area must be tiled much finer as has been done in existing approaches. The optimal tile grid can typically only be implemented by tiling the reconfigurable area into a two-dimensional grid. This will further increase the utilization of dedicated resources such as block RAMs. In order to provide communication with the reconfigurable modules, the novel ReCoBus communication architecture is enhanced for two-dimensional communication. A case study will demonstrate a system with 248 individual logic tiles that are each less than 200 LUTs in size while still being able of providing a module connection in each particular tile.

Advanced partial run-time reconfiguration on Spartan-6 FPGAs

In this paper, we demonstrate systems based on Spartan-6 series FPGAs that provide full support for active partial run-time reconfiguration. We will summarize design factors for successfully applying run-time reconfiguration, reveal details on partial reconfiguration on Spartan-6 FPGAs, and introduce our easy to use design flow. In this flow, a module can multiple times be instantiated or even migrated to different systems without the need to physically reimplement such a module. The demo systems can host manifold different partial modules that each are capable to manipulate a video stream.

An efficient FPGA overlay for portable custom instruction set extensions

Custom instruction set extensions can substantially boost performance of reconfigurable softcore CPUs. While this approach is commonly tailored to one specific FPGA system, we are presenting a fine-grained FPGA-like overlay architecture which can be implemented in the user logic of various FPGA families from different vendors. This allows the execution of a portable application consisting of a program binary and an overlay configuration in a completely heterogeneous environment. Furthermore, we are presenting different optimizations for dramatically reducing the implementation cost of the proposed overlay architecture. In particular, this includes the mapping of the overlay interconnection network directly into the switch fabric of the hosting FPGA. Our case study demonstrates an overhead reduction of an order of magnitude as compared to related approaches.