Jim Torresen

A Divide-and-Conquer Approach to Evolvable Hardware

Evolvable Hardware (EHW) has been proposed as a new method for designing systems for complex real world applications. One of the problems has been that only small systems have been evolvable. This paper indicates some of the aspects in biological systems that are important for evolving complex systems. Further, a divide-and-conquer scheme is proposed, where a system is evolved by evolving smaller subsystems. Experiments show that the number of generations required for evolution by the new method can be substantially reduced compared to evolving a system directly. However, there is no lack of performance in the final system.

FPGASort: a high performance sorting architecture exploiting run-time reconfiguration on fpgas for large problem sorting

This paper analyses different hardware sorting architectures in order to implement a highly scaleable sorter for solving huge problems at high performance up to the GB range in linear time complexity. It will be proven that a combination of a FIFO-based merge sorter and a tree-based merge sorter results in the best performance at low cost. Moreover, we will demonstrate how partial run-time reconfiguration can be used for saving almost half the FPGA resources or alternatively for improving the speed. Experiments show a sustainable sorting throughput of 2GB/s for problems fitting into the on-chip FPGA memory and 1 GB/s when using external memory. These values surpass the best published results on large problem sorting implementations on FPGAs, GPUs, and the Cell processor.

Efficient recognition of speed limit signs

An automatic traffic sign detection system is important in a driver assistance system. An approach for detecting Norwegian speed limit signs is proposed. It consists of three major steps: color-based filtering, locating sign(s) in an image and detection of numbers on the sign. About 91% correct recognition is achieved for a selection of 198 images.

Go Ahead: A Partial Reconfiguration Framework

Exploiting the benefits of partial run-time reconfiguration requires efficient tools. In this paper, we introduce the tool Go Ahead that is able to implement run-time reconfigurable systems for all recent Xilinx FPGAs. This includes in particular support for low cost and low power Spartan-6 FPGAs. Go Ahead assists during floor planning and automates the constraint generation. It interacts with the Xilinx vendor tools and triggers the physical implementation phases all the way down to the final configuration bit streams. Go Ahead enables the building of flexible systems for integrating many reconfigurable modules very efficiently into a system. The tool targets (re)usability, portability to future devices, and migration paths among reconfigurable systems featuring different FPGAs or even FPGA families. Moreover, it provides a scripting interface and all features can be accessed remotely.

A Survey of Self-Awareness and Its Application in Computing Systems

Novel computing systems are increasingly being composed of large numbers of heterogeneous components, each with potentially different goals or local perspectives, and connected in networks which change over time. Management of such systems quickly becomes infeasible for humans. As such, future computing systems should be able to achieve advanced levels of autonomous behaviour. In this context, the systems ability to be self-aware and be able to self-express becomes important. This paper surveys definitions and current understanding of self-awareness and self-expression in biology and cognitive science. Subsequently, previous efforts to apply these concepts to computing systems are described. This has enabled the development of novel working definitions for self-awareness and self-expression within the context of computing systems.

A Scalable Approach to Evolvable Hardware

Evolvable Hardware (EHW) has been proposed as a new method for designing systems for complex real-world applications. However, so far, only relatively simple systems have been shown to be evolvable. In this paper, it is proposed that concepts from biology should be applied to EHW techniques to make EHW more applicable to solving complex problems. One such concept has led to the increased complexity scheme presented, where a system is evolved by evolving smaller sub-systems. Experiments with two different tasks illustrate that inclusion of this scheme substantially reduces the number of generations required for evolution. Further, for the prosthesis control task, the best performance is obtained by the novel approach. The best circuit evolved performs better than the best trained neural network.

The Xilinx Design Language (XDL): Tutorial and use cases

With the Xilinx Design Language (XDL), the FPGA vendor Xilinx offers a very powerful interface that provides access to virtually all features of their devices. This includes on one side the generation of complete device descriptions containing information about the FPGA primitives and the routing fabric. On the other side, XDL can be used to constrain systems or to directly implement modules or macros for Xilinx FPGAs. In this paper, we will provide documentation on the language and reveal several use cases for this language.

A flexible on-chip evolution system implemented on a xilinx Virtex-II pro device

There have been introduced a number of systems with evolvable hardware on a single chip. To overcome the lack of flexibility in these systems, we propose a single-chip evolutionary system with the evolutionary algorithm implemented in software on a built-in processor. This architecture is implemented in a Xilinx Virtex-II Pro FPGA with an embedded PowerPC processor. This allows for a rapid processing of the time consuming parts in hardware and leaving other parts to more easily modifiable software. This platform will be beneficial for future work regarding both cost and compactness. Experiments have been performed on the physical device with software running in parallel with fitness computation in digital logic. The results show that the system uses only twice as much time when compared to a PC running at 10 times faster clock speed.

Evolving multiplier circuits by training set and training vector partitioning

Evolvable Hardware (EHW) has been proposed as a new method for evolving circuits automatically. One of the problems appearing is that only circuits of limited size are evolvable. In this paper it is shown that by applying an approach where the training set as well as each training vector is partitioned, large combinational circuits can be evolved. By applying the proposed scheme, it is shown that it is possible to evolve multiplier circuits larger then those evolved earlier.

High Speed Partial Run-Time Reconfiguration Using Enhanced ICAP Hard Macro

Achieving high speed run-time reconfiguration is important for the adaptation of partial reconfiguration in many applications. The reconfiguration speed that is currently available today is somehow artificially limited by the FPGA vendors, while the fabrication process technologies used for building the latest devices today are capable of achieving much higher reconfiguration speed. In this paper we will present a new design and implementation method for achieving high speed partial run-time reconfiguration that exceeds the specified reconfiguration speed of todays FPGAs. By adding custom logic around the Internal Configuration Access Port (ICAP) to implement an enhanced ICAP hard macro, we will investigate the partial run-time reconfiguration speed and explore the limits of the ICAP interface. This is done by using over clocking of the ICAP. Compared with previously work on high-speed reconfiguration, using the enhanced ICAP hard macro will significantly increase the reconfiguration speed.