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Dive into the research topics where Christian Gautier is active.

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Featured researches published by Christian Gautier.


international conference on electronic packaging technology | 2008

Moisture diffusion model verification of packaging materials

Xiaosong Ma; K.M.B. Jansen; L.J. Ernst; W.D. van Driel; O. van der Sluis; G.Q. Zhang; Charles Regard; Christian Gautier; Hélène Fremont

The use of the non-hermetic material for electronic packaging does raise a potential concern, i.e. moisture induced interfacial delamination and pop corning during reflow. Therefore, it is very important we can correctly model the moisture absorption property. In this study, moisture absorption and desorption properties of three kinds of package materials were investigated. Moisture absorption equilibrium weight gain and diffusion coefficient at different temperature and different humidity are characterized. Moisture absorption processes are simulated using a 3D model at conditions according to the moisture sensitivity test levels. Finally moisture absorption is verified by our research carrier.


Microelectronics Reliability | 2009

Fast reliability qualification of SiP products

Charles Regard; Christian Gautier; Hélène Fremont; Patrick Poirier; M.A. Xiaosong; Kaspar M. B. Jansen

For the purpose of rapidly identifying the functional weak points of SiP products and defining appropriate design rules, a new methodology is proposed to achieve fast reliability qualification. This new methodology is based on the moisture absorption behavior along the critical interface of a SiP carrier and on the most sensitive zone to delamination of the SiP carrier, determined by simulation and experimentally checked. In this paper, a new accelerated preconditioning is proposed and a new non destructive thermal method to monitor the delamination is presented. The effectiveness of this new stress test to accelerate the failure mechanism of the SiP carrier and the ability to detect delamination are evaluated by performing a DOE.


Microelectronics Reliability | 2008

Silicon based system in package: Improvement of passive integration process to avoid TBMS failure.

Christian Gautier; Sophie Ledain; Sébastien Jacqueline; Matthieu Nongaillard; Vincent Georgel; Karine Danilo

Because of its large dimension and its high level of integration, the PICS (Passive Integration Connecting Substrate) developed by NXP prone to top to bottom metal short (TBMS) failure during temperature cycling test. Several options of process modifications as well as new design rules and stress relief patterns for preventing TBMS failure are described. These countermeasures have been evaluated under high thermo-mechanical stress test. The results of these evaluations are also presented in this paper.


Microelectronics Reliability | 2010

A fast moisture sensitivity level qualification method

Xiaosong Ma; K.M.B. Jansen; G.Q. Zhang; W.D. van Driel; O. van der Sluis; L.J. Ernst; C. Regards; Christian Gautier; Hélène Fremont

In this paper, a fast moisture sensitivity level (MSL) qualification method and a fast moisture characterization method are discussed. The fast moisture characterization uses a stepwise method to obtain more reliable and more material moisture properties. The established relationships for moisture diffusion coefficients and moisture saturation levels with respect to the temperature and relative humidity can be used to predict moisture properties in the MSL range. Fast moisture sensitivity level qualification is accomplished with the aid of simulation combined with the characterized moisture diffusion properties. Moisture absorption processes at different conditions are simulated using a 3D model at conditions according to the moisture sensitivity test levels. Simulation of weight change at different condition and simulation of local moisture concentration are performed and compared between different conditions. Simulations show that at 696 h preconditioning time at 30 °C/60%RH for MSL level 2a can be decreased to 42 h at 85 °C/85%RH. Time required for package reliability and moisture sensitivity analysis is largely shortened.


international conference on electronic packaging technology | 2008

Influence of underfill methods on the solder joint fatigue of wafer level packaging

Charles Regard; Christian Gautier; Hélène Fremont; Patrick Poirier

To increase miniaturization, CSWLP (chip size wafer level packaging) has been developed. However, the difficulty to get good solder joint reliability leads to manufacture only small CSWLP modules. Different underfill methods are evaluated here, by measurements and simulations: results prove that underfill is necessary, but a bad choice can also decrease the reliability. An original method called ldquore-enforcementrdquo improves the life time.


international conference on electronic packaging technology | 2009

Fast qualification using thermal shock combined with moisture absorption

Xiaosong Ma; G.Q. Zhang; K.M.B. Jansen; W.D. van Driel; O. van der Sluis; L.J. Ernst; Charles Regard; Christian Gautier; Hélène Fremont

Time to market is becoming one of the most important factors because of the fierce market competition. However, traditional reliability and interface toughness characterization tests take very long time. For example, moisture sensitivity level assessment (MSL1) will take 168 hours pre conditioning at 85°C/85%RH and tradition thermal cycling takes even longer time. The long preconditioning times are chosen to ensure that also the thicker sections of a package are completely saturated. Thinner package, however, are already saturated after one to two days. In this study, we therefore investigated whether it would be possible to speed up the qualification process by shortening the preconditioning time. We focus in particular on the interface toughness. From our four point bending test and analysis, it is found that temperature has great effects on the interface toughness and moisture also has small effects on the interface toughness. In order to do the fast qualification test, thermal shock cycling tests combined with moisture absorption are performed. Experiments show that moisture can speed up the delamination.


international conference on thermal mechanial and multi physics simulation and experiments in micro electronics and micro systems | 2008

Effect of aging of packaging materials on die surface cracking of a SiP carrier

Xiaosong Ma; K.M.B. Jansen; L.J. Ernst; W.D. van Driel; O. van der Sluis; G.Q. Zhang; Charles Regard; Christian Gautier; Hélène Fremont

Generally, the viscoelastic properties of packaging materials used in the simulation models are obtained from the materials after postcuring. However these properties were observed to change during humidity conditioning and the thermal cycling. Two kinds of packaging materials are tested, one is molding compound and another is underfill. All samples are cured according to the curing procedure, postcured at 180degC. Before the test, first the samples are pre-dried at 125degC for 24 hours and then preconditioned at 60degC/60%RH for 40 hours. Secondly, one reflow at 260degC. Finally, all samples are subjected to thermal cycling. Thermal cycling temperature range is from -65degC to 150degC and every cycle is finished in 30 minutes. For the DMA test, a TA Instrument Q800 is used. Test results show the glass modulus, rubber modulus and glass transition temperature increase with the number of thermal cycles. This change in materials after humidity and thermal treatment is here referred to as aging. The finite element software Marc is used to simulate the internal change of stress and displacement. The simulation result shows that the total warpage has increased a little at the corner of passive die, which is where the critical cracks and crazes were found in our qualification tests. And the Von Mises stresses increase after thermal cycling.


international conference on thermal, mechanical and multi-physics simulation and experiments in microelectronics and microsystems | 2010

Die attach interface property characterization as function of temperature using cohesive zone modeling method

Xiaosong Ma; G.Q. Zhang; O. van der Sluis; K.M.B. Jansen; W.D. van Driel; L.J. Ernst; Charles Regard; Christian Gautier; Hélène Fremont

Interface delamination is one of the most important issues in the microelectronic packaging industry. Silver filled die attach is a typical adhesive used between the die and copper die pad for its improved heat dissipation capacity. Delamination between die attach and die pad will severely impact the heat conduction and result in product failure. In order to predict this delamination, interface properties should be characterized. Tri-material, copper-die attach-EMC, samples are made according to the package processes. A four point bending test system is established in order to perform delamination tests at different temperatures using a universal tester Zwick/Roell Z005. In addition, a Keyence optical system is mounted to capture a series of pictures during the delamination processes. This will provide the delamination geometry information needed for determining the interface properties. Four point bending tests have been performed at room temperature, 40, 60, 85, and 150?C respectively. In addition pre conditioning sample are also tested at room temperature and 85?C respectively after 48 hours pre conditioned at 85?C/85%RH. Experiments show that the ?critical delamination load? decreases steadily with temperature increasing. Experiments also show moisture has no effects on the ?critical delamination load? compared with the dry samples tested at the same temperatures. This means that moisture has no effects on the interface toughness between copper and die attach. To quantify the interface properties, numerical simulations of the four point bending test have been performed by using a finite element model comprising cohesive zone elements which will describe the transient delamination process during the four point bending tests. Correspondently, the interface toughness decreases from 26.5J/m2 at room temperature to 1.9J/m2 at 150?C as calculated from the cohesive zone element model. These results show that temperature has a large effect on the interface toughness. By means of an extensive model parameter sensitivity study, combined with the measured delamination length in horizontal direction along the copper-die attach interface at room temperature critical opening value has been determined.


international conference on thermal mechanial and multi physics simulation and experiments in micro electronics and micro systems | 2008

Solder fatigue of Wafer Level package assemblies. Comparison with flip chip BGA’S

Charles Regard; Christian Gautier; Hélène Fremont; Alexandre Val; Frederic Roullier; Patrice Schwindenhammer; Patrick Poirier

In this paper the solder fatigue of WLCSP (wafer level chip scale packages) assemblies is studied and a comparison with flip chip BGA is made. Previous works have already shown that for BGA, the most critical parameters are size, thickness, and underfill. We have evaluated both by thermal cycling and by simulations the effect of thickness and underfill in the WLCSPs case. WLCSP devices with a size of 13mm2 were stressed up to 1500 cycles to emphasize the BGA like failures and evaluate the behavior of this new technology. We have demonstrated that the same failure mechanisms occur in BGA and in WLCSP. We also highlight the criticality of the WLCSP regarding industrial assembly process on board.


Microelectronics Reliability | 2009

Correlation between EOS customer return failure cases and Over Voltage Stress (OVS) test method.

Jean Luc Lefebvre; Christian Gautier; Frédéric Barbier

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G.Q. Zhang

Delft University of Technology

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L.J. Ernst

Delft University of Technology

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W.D. van Driel

Delft University of Technology

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K.M.B. Jansen

Delft University of Technology

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Xiaosong Ma

Delft University of Technology

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O. van der Sluis

Delft University of Technology

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Kaspar M. B. Jansen

Delft University of Technology

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