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Featured researches published by W.D. van Driel.


Archive | 2006

Mechanics of microelectronics

G.Q. Zhang; W.D. van Driel; Xuejun Fan

Microelectronics technology Introduction A heart of silicon In a little black box Baseline CMOS Non-CMOS options Packaging Systems Conclusions References Nomenclature Reliability practices Introduction Reliability assessment Reliability statistics Acceleration factor models Failure mechanisms Conclusions References Exercises Thermal Management Introduction Heat transfer basics Thermal design of assemblies Thermal design for a SQFP Heatsink design choices Conclusions / final remarks References Introduction to Advanced Mechanics Introduction Stress and strain Failure criteria Fracture mechanics Finite element method References Exercises Thermo-Mechanics of Integrated Circuits and Packages Introduction IC Backend and packaging processes and testing Thermo-mechanics of IC backend processes Thermo-Mechanics of packaging processes Thermo-Mechanics of coupled IC backend and packaging processes Case studies References Exercises Characterization and Modeling of Moisture Behavior Introduction Moisture diffusion modeling Characterization of moisture diffusivity and saturation concentration Vapor pressure modeling Hygroscopic swelling characterization & modeling Single void Instability behavior Subjected to vapor pressure and thermal stress Interface strength characterization and modeling Case studies References Exercises Characterization and Modeling of Solder Joint Reliability Introduction Analytical-empirical prognosis of the reliability Thermo-mechanical characteristics of soft solders Data evaluation and LIFE-time estimation Case studies References Exercises Virtual thermo-mechanical prototyping Introduction The state-of-the-art of virtual prototyping Case studies Conclusions References Exercises Challenges and future perspectives Introduction Product and process inputs Tests and experiments Multi-scale mechanics Advanced simulation tools Multi-physics modeling Material and interface behavior Simulation-based optimization Conclusions


IEEE Transactions on Components and Packaging Technologies | 2008

Interfacial Delamination Mechanisms During Soldering Reflow With Moisture Preconditioning

Xuejun Fan; G.Q. Zhang; W.D. van Driel; L.J. Ernst

This paper first examines the commonly-used thermal-moisture analogy approach in thermal-moisture analogy approach. We conclude that such an analogy using a normalized concentration approach does not exist in the case of soldering reflow, when the solubility of each diffusing material varies with temperature or the saturated moisture concentration is not a constant over an entire range of reflow temperatures. The whole field vapor pressure distribution of a flip chip BGA package at reflow is obtained based on a multiscale vapor pressure model. Results reveal that moisture diffusion and vapor pressure have different distributions and are not proportional. The vapor pressure in the package saturates much faster than the moisture diffusion during reflow. This implies that the vapor pressure reaches the saturated pressure level in an early stage of moisture absorption, even the package is far from moisture saturated. However, the interfacial adhesion degrades continuously with moisture absorption. Therefore, the package moisture sensitivity performance will largely reply on the adhesion strength at elevated temperature with moisture. A specially designed experiment with a selection of six different underfills for flip chip packages was conducted. Results confirm that there is no correlation between moisture absorption and the subsequent interface delamination at reflow. The adhesion at high temperature with moisture is the only key modulator that correlates well with test data. Such a parameter is a comprehensive indicator, which includes the effects of thermal mismatch, vapor pressure, temperature and moisture. In this paper, a micromechanics based mechanism analysis on interfacial delamination is also presented. With the implementation of interface properties into the model study, it shows that the critical stress, which results in the unstable void growth and delamination at interface, is significantly reduced when the effect of moisture on debonding is considered.


Microelectronics Reliability | 2003

Prediction and verification of process induced warpage of electronic packages

W.D. van Driel; G.Q. Zhang; J.H.J. Janssen; L.J. Ernst; Fei Su; Kerm Sin Chian; Sung Yi

Abstract During the manufacturing, testing and service, thermally induced deformations and stresses will occur in IC devices and packages, which may cause various kinds of product failures. FEM techniques are widely used to predict the thermal deformations and stresses and their evolutions. However, due to the complexity of the real engineering problems, various assumptions and simplifications have to be made in conducting FEM modelling. Therefore, the applicability of the predicted results depend strongly on the reliability and accuracy of the developed FEM-based prediction models which should be verified before applications. In this paper, FEM models are developed to predict the thermal deformations of certain electronic packages and naked die samples under packaging and testing loading. For all the package constituents, appropriate material properties and models are used, including temperature-dependent visco-elasticity, anisotropy, and temperature-dependent elasticity and plasticity. To verify the developed FE models, a series of optical metrology tests are performed. A compact 3D interferometry testing system that can measure simultaneously out-of plane and in-plane deformations has been developed. Thermal deformation measurements are performed on samples of both real electronic packages and naked dies attached on a leadframe. Identical deformation patterns were found for the measured fringe patterns in the U -, V -, and W -fields and the simulated ones. Also, quantitatively, the maximum deformation mismatch between the predicted and tested results is within 15%. It is concluded that the thermally induced deformations predicted by the non-linear FEM models match well with measured deformations for both the naked die and the real packages.


Microelectronics Reliability | 2009

Advances in the drop-impact reliability of solder joints for mobile applications

E. H. Wong; S.K.W. Seah; W.D. van Driel; J.F.J.M. Caers; N. Owens; Y.-S. Lai

This manuscript presents the research studies in the drop-impact reliability of solder joints in the PCB assemblies intended for mobile applications. The works cover stress–strain characterisation of solders, evaluation of test methods at component and board levels, and investigation of the fatigue characteristics of solder joints. The stress–strain characteristics of four solder alloys were generated for the low and medium strain rate regimes up to the strain rate of 300 s � 1 . In the study on test methods, the board level high speed cyclic bend test and the component level ball impact shear test were correlated with the board level drop-shock test using 23 groups of diverse solder joints. The high speed cyclic bend test was found to be able to replicate the failure mode and the performance ranking of the solder joints in the board level drop-shock test, while the ball impact shear test was found to have poor correlation with the board level drop-shock test. The S–N characteristics of solder joints between the PCB fibre strains of 1 � 10 � 3 to 3 � 10 � 3 , as a function of bending frequency (from 30 to 150 Hz) and test temperatures (�10 C and 25 C), were generated. The propagation of cracks in the solder joints were monitored through electrical resistance measurement, and the rates of propagation were correlated with the observed crack paths in the solder joints. The effects of load history on crack propagation were investigated using two-step load tests, and the use of Miner’s rule was found to be non-conservative. Design rules were formulated based on analytical solutions, and a robust solder joint design was proposed and validated.


Microelectronics Reliability | 2006

Facing the Challenge of Designing for Cu/Low-k Reliability

W.D. van Driel

This paper highlights some of the solutions for the typical reliability problems faced during the development of the Cu/low-k technology that were needed to overcome the problems encountered throughout the complete manufacturing process from IC front-end to packaging back-end


IEEE Transactions on Components and Packaging Technologies | 2008

Driving Mechanisms of Delamination Related Reliability Problems in Exposed Pad Packages

W.D. van Driel; M.A.J. van Gils; Xuejun Fan; G.Q. Zhang; L.J. Ernst

Exposed pad packages were introduced in the late 1980s and early 1990s because of their excellent thermal and electrical performance. Despite these advantages, the exposed pad packages experience a lot of thermo-hygro-mechanical related reliability problems during qualification and testing. Examples are die lift, which occurs predominantly after moisture sensitivity level conditions, and die-attach to leadframe delamination leading to downbond stitch breaks during temperature cycling. In this chapter, nonlinear finite element (FE) models using fracture mechanics based J-integral calculations are used to assess the reliability problems of the exposed pad package family. Using the parametric FE models any geometrical and material effects can be explored to their impact on the occurrence diepad delamination, and dielift. For instance the impact of diepad size is found to be of much less importance as the impact of die thickness is. Using the fracture mechanics approach, the starting location for the delamination from thermo-hygro-mechanical point of view is deducted. The results indicate that when diepad delamination is present, cracks are likely to grow beneath the die and dielift will occur. The interaction between dielift and other failure modes, such as lifted ball bonds, are not found to be very significant. The FE models are combined with simulation-based optimization methods to deduct design guidelines for optimal reliability of the exposed pad family.


electronic components and technology conference | 2004

Prediction of process-induced warpage of IC packages encapsulated with thermosetting polymers

D.G. Yang; K.M.B. Jansen; L.J. Ernst; G.Q. Zhang; W.D. van Driel; H.J.L. Bressers; Xuejun Fan

One critical issue for manufacturing of map-molded packages is the warpage induced during the molding process. A cure-dependent viscoelastic constitutive model has been established to describe the evolution of material properties during the curing process of a thermosetting polymer. The evolution of the rubbery moduli is described by a model based on scaling analysis and is measured with a new method. The relaxation behavior of the transient part is described by the cure-dependent relaxation amplitude and reduced relaxation times which are based on the time-conversion superposition principle. The cure-dependent parameters are characterized by using an combinational approach of DMA and DSC measurements. The predictions agree well with the experimental results. FEM is conducted for QFN map molding processes, and prediction of the warpage induced during the curing process and the cooling down is made. The results show that warpage induced during the curing process has a significant contribution on the total warpage. Furthermore, when decreasing the number of maps, the contribution of curing-induced warpage significantly increases.


Microelectronics Reliability | 2008

Correlation studies for component level ball impact shear test and board level drop test

E. H. Wong; Ranjan Rajoo; S.K.W. Seah; C. S. Selvanayagam; W.D. van Driel; J.F.J.M. Caers; X. J. Zhao; N. Owens; L.C. Tan; M. Leoni; P. L. Eu; Y.-S. Lai; C.-L. Yeh

This paper presents a comprehensive study of the resistance of solder joints to failure when subjected to strain rates that simulate the conditions of drop-impact on a portable electronic product. Two test methods are used in this study: the board level drop/shock test (BLDT) and the component level ball impact shear test (BIST). The performance of (i) 12 material combinations consisting of six solder alloys and two pad finishes; and (ii) 11 manufacturing variations covering three vendors, two finishes, three immersion gold thicknesses and three thermal aged conditions, were investigated using these two test methods, and analysis of correlations between the methods was performed. Quantitative correlation and sensitivity coefficients for the failure modes and the measured characteristic parameters – number of drops to failure for BLDT and peak load, total fracture energy, and energy-to-peak load for BIST – were evaluated. The lack of universal correlations between the two test methods has ruled out the use of BIST for evaluating solder joint materials, but BIST is recommended as a test method for quality assurance in view of the strong correlation between the measured parameters and the failure mode. The total fracture energy parameter is preferred over the peak load and energy-to-peak load due to its higher sensitivity and reduced susceptibility to measurement error.


Microelectronics Reliability | 2007

Numerical modeling of warpage induced in QFN array molding process

D.G. Yang; Kaspar M. B. Jansen; L.J. Ernst; G.Q. Zhang; W.D. van Driel; H.J.L. Bressers; J.H.J. Janssen

Warpage is a critical issue for QFN array molding process. In this paper, a cure-dependent viscoelastic constitutive model is established to model the cure-induced warpage in array molding process. For the relaxation modulus functions of the packaging polymer, the equilibrium moduli are modeled with a model based on scaling analysis and the relaxation behavior of the transient part is described by the cure-dependent relaxation amplitude and reduced relaxation times which are based on the time-conversion superposition principle. The cure-dependent parameters are characterized by using an integrated approach of dynamical mechanical analysis (DMA) and differential scanning calorimetry (DSC) measurements. Finite element modeling is carried out for three configurations of a carrier package map mould and the warpage induced during the curing process and cooling down is predicted. The results show that warpage induced during the curing process has significant contribution on the total warpage of the map.


Microelectronics Reliability | 2005

Prediction of delamination related IC & packaging reliability problems

W.D. van Driel; M.A.J. van Gils; R.B.R. van Silfhout; G.Q. Zhang

Abstract This paper presents our effort to predict delamination related IC & packaging reliability problems. These reliability problems are driven by the mismatch between the different material properties, such as thermal expansion, hygro-swelling, and/or the degradation of interfacial strength. First of all, a test technique is presented to measure the interfacial strength between packaging materials. Secondly, several reliable non-linear Finite Element models are developed, able to predict the reliability impact of delamination on wire failures, different package structures, and passivation cracks in IC-packages.

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G.Q. Zhang

Delft University of Technology

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L.J. Ernst

Delft University of Technology

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G.Q. Zhang

Delft University of Technology

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K.M.B. Jansen

Delft University of Technology

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M. Yazdan Mehr

Delft University of Technology

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O. van der Sluis

Delft University of Technology

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J.J.M. Zaal

Delft University of Technology

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