Christian Gontrand

A Simple Way for Substrate Noise Modeling in Mixed-Signal ICs

Here is a complete methodology of substrate noise modeling. The aim of this study is to predict the perturbations induced by digital commutations flowing through the substrate to reach sensitive analog blocks. Till now, the studies have only taking into account the parasitic elements of the bonding wires. This work consists of each part of a mixed-signal design that induces power-and-ground bounces: the printed circuit board, the package, the bonding wires, the input-output ring, the on-chip power-supply distribution, and the digital core of the chip. A standard approach, called integrated circuit (IC) emission model, is used to create the substrate simulation model. By adding some elements to this power-supply model, we can simulate the transient substrate voltage induced by the digital part of a mixed-signal IC. A test chip has been realized in a 0.35-mum BiCMOS process to validate this substrate coupling model. Power-supply network, chip activity and substrate propagation of this circuit are obtained by using classical computer-aided design tools. Some Spice simulations of the modeled test chip, running in many different configurations, are shown. Comparisons between measurements and simulations are done and lead to the conception of an optimized version of the same circuit that induces less parasitic substrate voltages

Modelling of through silicon via and devices electromagnetic coupling

This paper is essentially composed of two parts for future synthesis. We developed 2D and 3D simulations, starting from a 0.35µm standard CMOS technology, focusing on through silicon via or redistribution layer induced coupling; nMOSFET, pMOSFET, and the sensitive regions of the CMOS inverter are investigated. We also study stacked devices in 3D circuits, in the radiofrequency range, and propagation of electromagnetic waves along some interconnections with discontinuities. This study is performed in the time domain-a finite-difference time-domain method is applied to the analysis of some vias flanked by two striplines, all embedded in silicon. Electric and magnetic field distributions, transmission and reflexion parameters, and pulse propagations along a transverse via are presented.

Flexible test bed for the behavioural modelling of power amplifiers

Purpose – The paper aims to focus on the memory-polynomial model (MPM) as special case of Volterra series, implemented in hardware. The behavior of the MPM is fully proved through a comparison with AM-AM and AM-PM measured data. The results show that this simulation technique is able to prove the effectiveness of the MPM implementation as behavioural model for high power radiofrequency amplifiers. The system is able to compensate perturbations caused by modern communication systems. Design/methodology/approach – The implementation uses Matlab-Simulink, and its digital signal processing (DSP) builder. The first stage allows developing the model in Matlab using the DSP builder blockset through the signal compiler block. Then, the design is downloaded to the DSP board. Findings – The paper demonstrates a proper behavior of the MPM as a truncation of the Volterra series, with respect to different inputs. This is a key point, because the series truncations allow first to implement this model in real time and s...

Analysis of low energy boron implants in silicon through SiO2 films: implantation damage and anomalous diffusion

Abstract The experimental investigation reported in this paper focuses on the effect of induced implantation damage on the boron diffusion process. Boron is implanted at various fluences and energies in Cz-(100) silicon through different oxide layer thicknesses. Rapid thermal Annealing (RTA) is used to activate shallow p+ layers (0·1–0·15 μm) following boron implantations Concentrations versus depth boron profiles are measured using a secondary ion mass spectrometry (SIMS) analyser. An enhanced boron diffusion is detected in the tail region when the oxide thickness decreases. If the concentration peak is located at the oxide/silicon interface or in the substrate, further implantation damage is generated. This observed enhanced boron diffusion is thus attributed to the implantation-induced damage. The point defects, which act as a driving force for this enhanced boron diffusion at different annealing stages, are detected by the deep level transient spectroscopy (DLTS) technique. In particular, the effect of knocked-on oxygen during the implantation step on the generation of deep centres and defects is investigated. Finally, all the results reveal that DLTS coupled to SIMS analysis provides an efficient method with which to identify the origin and the nature of implanted and RTA related defects.

A high-performance lateral PNP transistor structure

This paper proposes a novel lateral PNP-type structure that is fully compatible with existing single-polysilicon BiCMOS processes and offers a valid alternative to shallow polysilicon emitter transistors. We have used both an analytical approach and a more accurate computer-aided design, obtaining 0.9 GHz and 4.4 GHz cutoff frequency for 2 /spl mu/m and 0.8 /spl mu/m minimum feature transistors, respectively.

Simulating the Long Term Evolution (LTE) Downlink Physical Layer

In this paper we investigate a comprehensive analysis of Long Term Evolution Advanced (LTE) downlink (DL) physical layer performance using Multi Input Multi Output channel (MIMO) based on standard parameters. The work consists firstly in modeling LTE physical downlink shared channel (PDSCH). The developed model is based on an independent functional blocks in order to facilitate reproduction of signal processing techniques results used in LTE and particularly to evaluate the physical layer downlink components. Thereafter, it was integrated in the simulator, basic structure with AWGN channel including evaluation of using diversity and spatial multiplexing transmissions on downlink connections and multipath fading channel model. The simulation examples are illustrated with different digital modulation and MIMO scheme. BER and throughput results with multipath impact on transmission channel quality are also considered. These results show that the model implemented in Matlab faithfully advantages introduced in the LTE system.

Modeling memory effects in RF power amplifiers applied to a digital pre-distortion algorithm and emulated on a DSP-FPGA board

An emulation tool with the capability of modeling the nonlinearity order and memory effects for real power amplifiers (PAs) conversion curves, is introduced. The proposed tool comprises special cases of Volterra series as the Memory Polynomial Model and a learning technique like artificial neural networks. The proposed system is a novel integrated one able to model the real behavior of radio frequency (RF)-PAs under different memory models. The developed system starts from a test bed able to acquire AM-AM and AM-PM distortion curves measurements. This procedure can predict the behavior and improve the analysis using it as a design tool. Emulation tool for modeling the nonlinearity order and memory effects for real power amplifiers.It comprises Memory Polynomial Model and a learning technique like artificial neural networks.The new proposed tool reduces design time as well as realizing the implementation of a DPD.The overall performances have been properly verified by using AM as input signals.A novel technique by combining a GUI as control stage, Simulink and the DSP Builder tool.

Impact of substrate perturbation on a 5 GHz VCO spectrum

This work investigates substrate coupling effects in mixed ICs, especially the perturbations on RF block. The authors present the impact of low frequency substrate noise perturbations on voltage-controlled oscillator (VCO) spectrum. A 5 GHz VCO test-chip is presented; several substrate taps have been placed inside VCO core to measure or to inject noise perturbations. The oscillation frequency sensitivity function of tuning voltage or bias current and spurious side-bands due to injected noise are measured to find out a relation between substrate noise and spectrum purity. Finally, a significant link between such device sensitivity functions and VCO spurs magnitude is demonstrated.

On a standard approach for substrate noise modelling in mixed signal IC's

An alternative way of using the ICEM model is described. This model is considering each part of a mixed signal design: the PCB, the package, the bonding wires, the padring and the core of the digital chip. By adding some elements to this model, we can simulate the transient substrate voltage induced by the digital part of a mixed signals integrated circuit. A test-chip was implemented in a 0.35 /spl mu/m BiCMOS process to validate this extended ICEM model. Some spice simulations of the modelled test-chip, running in many different configurations, are exposed. The results of those simulations are compared to measurements and reveal the advantages and drawbacks points of the methodology. We also describe what has to be done to apply this method to a realistic digital circuit.

The effect of rapid thermal treatments on the formation of shallow junctions by implanting boron and BF2+ ions into (100) silicon through a protecting mask

Abstract The effect of rapid thermal annealing (RTA) on the formation of shallow p + n junctions by the implantation of boron (11B+) and boron difluoride (BF2+) ions into SiO 2 Cz-(100) Si systems have been studied. The junction formation by various implant conditions have been investigated to correlate with initial dopant drive-in efficiency, defects in junctions, and junction depth under different anneal experimental conditions. Boron and fluorine concentrations versus depth profiles before and after annealing have been measured using secondary ion mass spectrometry (SIMS). Results indicate that boron diffusion in the BF2+ case is widely reduced during rapid thermal treatments. Discussions of this are based on the effect of both knocked-on oxygen and fluorine on the boron diffusion kinetics.