Christian Hennesthal

Grain structure analysis and effect on electromigration reliability in nanoscale Cu interconnects

The grain structure in Cu interconnects of the 45 nm node was analyzed to yield grain orientation and boundary characteristics using a high-resolution electron diffraction technique. A dominant sidewall growth of {111} grains was observed, reflecting the importance of interfacial energy in controlling grain growth below 70 nm linewidth. The grain structure was used to identify flux divergent sites for void formation under electromigration (EM) and to analyze the effect on EM statistics for Cu lines with CoWP capping using a microstructure-based model. This analysis established a correlation between the microstructure of Cu nanolines, void formation kinetics, and EM statistics.

Electromigration early failure void nucleation and growth phenomena in Cu and Cu(Mn) interconnects

Electromigration early failure void nucleation and growth phenomena were studied using large-scale, statistical analysis methods. A total of about 496,000 interconnects were tested over a wide current density and temperature range (j = 3.4 to 41.2 mA/μm2, T = 200 to 350°C) to analyze the detailed behavior of the current density exponent n and the activation energy Ea. The results for the critical V1M1 downstream interface indicate a reduction from n = 1.55±0.10 to n = 1.15±0.15 when lowering the temperature towards 200°C for Cu-based interconnects. This suggests that the electromigration downstream early failure mechanism is shifting from a mix of nucleation-controlled (n = 2) and growth-controlled (n = 1) to a fully growth-controlled mode, assisted by the increased thermal stress at lower temperatures (especially at use conditions). For Cu(Mn)-based interconnects, a drop from n = 2.00±0.07 to n = 1.64±0.2 was found, indicating additional effects of a superimposed incubation time. Furthermore, at lower current densities, the Ea value seems to drop for both Cu and Cu(Mn) interconnects by a slight, but significant amount of 0.1 - 0.2eV. Implications for extrapolations of accelerated test data to use conditions are discussed. Furthermore, the scaling behavior of the early failure population at the NSD=-3 level (F~0.1%) was analyzed, spanning 90, 65, 45, 40 and 28 nm technology nodes.

Effects of cap layer and grain structure on electromigration reliability of Cu/low-k interconnects for 45 nm technology node

The effects of cap layer and grain structure on electromigration (EM) reliability of Cu/low-k interconnects were investigated for the 45 nm technology node. Compared to the SiCN cap only, the CoWP capped samples showed a 40x lifetime improvement with a small lifetime variation (σ=0.34) at the M1 level. By tuning the process parameter, Cu lines of two different grain sizes were fabricated at the M2 level for both with and without the CoWP cap. The EM results showed that, for both caps, the Cu lines with the large grain structure had a longer EM lifetime compared with the small grain structure, and the EM enhancement of the metal cap was reduced for the small grain structure. Failure analysis revealed two failure modes for the SiCN cap, with void formation either at the via corner or in the trench away from the via; on the contrary, voids mostly formed several microns away from the via for the large grain CoWP cap. The difference in voiding locations for the two caps was attributed to the different interfacial mass transport rate. Implications of scaling effect on EM reliability were also discussed.

Process options for improving electromigration performance in 32nm technology and beyond

In this paper we present process options to close the gap between electromigration performance needs by design and process performance. We are going to present reliability data for metal capping and advanced copper surface cleaning processes. These processes are showing very good performance and extendibility to 32nm technology nodes and beyond.

Grain Size And Cap Layer Effects On Electromigration Reliability Of Cu Interconnects: Experiments And Simulation

This paper combined experiments and simulation to investigate the grain size and cap layer effects on electromigration (EM) reliability of Cu interconnects. First the statistical distribution of EM lifetime and failure modes were examined for in laid Cu interconnects of large and small grain structures with two different cap layers of SiCN vs. CoWP. The CoWP cap was found to significantly improve the EM lifetime due to the suppression of the interfacial mass transport as a result of strengthening of the Cu/cap interface bonding. In addition, the grain size was observed to affect the EM reliability significantly, particularly for the CoWP capped structures. Resistance traces and failure analysis revealed two distinct failure modes: mode I with voids formed near the cathode via corner and mode II with voids formed in the trench several microns away from the cathode via. It was found that large grain size and strong cap interface reduced the mass transport rate and the void diffusion in the Cu line, leading ...

An experimental methodology for the in-situ observation of the time-dependent dielectric breakdown mechanism in Copper/low-k on-chip interconnect structures

This study captures the time-dependent dielectric breakdown kinetics in nanoscale Cu/low-k interconnect structures, applying in-situ transmission electron microscopy (TEM) imaging and post-mortem electron spectroscopic imaging (ESI). A “tip-to-tip” test structure and an experimental methodology were established to observe the localized damage mechanisms under a constant voltage stress as a function of time. In an interconnect structure with partly breached barriers, in-situ TEM imaging shows Cu nanoparticle formation, agglomeration and movement in porous organosilicate glasses. In a flawless interconnect structure, in-situ TEM imaging and ESI mapping show close to no evidence of Cu diffusion in the TDDB process. From the ESI mapping, only a narrow Cu trace is found at the SiCN/OSG interface. In both cases, when barriers are breached or still intact, the initial damage is observed at the top interface of M1 between SiCN and OSG.

Analysis of grain structure by precession electron diffraction and effects on electromigration reliability of Cu interconnects

In this paper, a recently developed high resolution electron diffraction technique is employed to characterize the grain orientation and grain boundaries for 45 nm node Cu interconnects with SiCN capping. The results are applied to evaluate the grain structure effect on electromigration (EM) reliability. We first calculate the flux divergence for void formation using interfacial and grain boundary diffusivities extracted from the resistance evolution of test structures observed during EM tests. To further correlate grain structure statistics with EM failure statistics, the EM lifetime distribution for Cu interconnects with CoWP capping is analyzed using a microstructure-based statistical model.

Backend-of-line reliability improvement options for 28nm node technologies and beyond

This paper reviews the most encouraging process options for improving backend-of-line reliability performance in advanced technology nodes. Metal capping yields the best electromigration performance; however, this process is most challenging with respect to integration and may also suffer from significantly decreasing grain sizes in trench bottoms for future technologies. Furthermore, time-dependent dielectric breakdown has to be carefully evaluated. Alloying or silicidation techniques are less challenging to implement but can result in unacceptably high resistance increases. We analyze the respective results for each option and compare the performance on 45, 32, and 28nm technology nodes. In addition to electromigration and time-dependent dielectric breakdown, the impact of the various process options on stress migration performance is discussed.

Comparison of Process Options for Improving Backend-of-Line Reliability in 28 nm Node Technologies and Beyond

This paper compares the most encouraging process options for improving electromigration performance in advanced technology nodes. Metal capping yields the best electromigration performance; however, this process is most challenging with respect to integration and may also suffer from significantly decreasing grain sizes in trench bottoms for future technologies. Alloying or silicidation techniques are less challenging to implement but can result in unacceptably high resistance increases. We analyze the respective results for each option and compare the performance on 45, 32, and 28 nm technology nodes. In addition, the impact of the various process options on stressmigration and time-dependent dielectric breakdown are discussed.

Cap layer and grain size effects on electromigration reliability in Cu/low-k interconnects

Downstream electromigration (EM) study was performed to investigate the cap layer and the grain size effects on Cu EM reliability for the 45 nm technology node. Four sets of Cu interconnects were examined: large and small grains with and without a CoWP cap placed between the SiCN cap and the Cu lines. Without the CoWP cap, the EM lifetime was reduced by a factor of 1.9 when changing from large to small grain structures and with the CoWP cap, this effect became more significant with EM lifetime reducing from >100x to ∼24x. Failure analysis showed two types of failure modes with distinct step-like resistance increases and voiding locations in Cu trench lines, reflecting the grain structure effect on void formation and EM statistics. A statistical simulation based on the Monte Carlo method was used to investigate the grain size and cap layer effects. The results were consistent with the experimental observations and the implication on EM reliability for future interconnects was discussed.