Christian Kerstan

Efficient Architecture Evaluation Using Functional Mapping

For an efficient design flow the substantiation of early design decisions is obligatory. This implies a simple and fast architecture evaluation using simulative approaches. This paper introduces an approach which enables a powerful hardware/software partitioning and the reuse of already existing functional code by applying minimal code modifications only. The primary objective is to provide a solution to enable an automated application. In this novel approach, code readability and transformation effort are improved significantly by using the powerful operator overloading mechanism of C++. The implementation can easily be customized and combined with other approaches concerning simulative design evaluations. For example, it is possible to realize implicit timing behavior, transparent communication over module boundaries, tracing of simulation data or collecting debugging information.

Enabling automated code transformation and variable tracing

To solve the challenge of hardware/software partitioning and the reuse of legacy system models (Bannow et al., 2004) introduced a module adapter (MA) based approach which is considered in section 2. The described transformation/mapping of functional code into a SystemC model still needs heavy code modifications. Besides the parser that has to be nearly as powerful as a C++ compiler the readability suffers from the necessary changes. This paper introduces an approach which reduces the code modifications to a minimum. The primary objective is to provide a solution to enable an automated application. In this novel approach, code readability and transformation effort are improved significantly by using the powerful operator overloading mechanism of C++. The presented implementation can be used to either realize transparent communication over module barriers, trace simulation data or only for debugging purposes. Some examples demonstrate the applicability and give some incitements for expedient use cases. The presented C++ code can be easily extended by inheritance for custom needs.

A Framework for Interactive Refinement of Mixed HW/SW/Analog Systems

Increasing complexity and heterogeneity leads to systems that combine the aspects of both digital hardware/software and mixed-signal embedded systems. A major difficulty is the fact that the components for mixed-signal systems are designed bottom-up, while a digital hardware/software system is designed top- down. Often this requires co-simulation, in practice involving multiple simulators from different vendors and on different platforms. Unfortunately, setting up co-simulations is a time-consuming task which is therefore done only a few times for verification purposes. In this paper we show how a plain SystemC simulation can be connected to Saber. A proxy module interfaces to the SystemC simulation and relays signals from and to Saber. A special signal synchronisation and update scheme ensures the availability of current analogue values to SystemC starting from the very beginning of each time step. Furthermore we introduce a mechanism for automatically connecting SystemC modules and show how it can be used to implement a graphical SystemC editor. A design example which compares a SystemC to Saber co-simulation to a functionally identical SystemC-AMS simulation is also included.