Nico Bannow

Analogue mixed signal simulation using Spice and SystemC

SystemC is a discrete event simulator that enables the programmer to model complex designs with varying levels of abstraction. In order to improve precision, it can be coupled to more specialized simulators. This article introduces the concept of loose simulator coupling between an analogue simulator and SystemC. It explains the properties and advantages which include a higher simulation performance as well as a higher degree of flexibility. A design example in which SystemC will be connected to SwitcherCad will demonstrate the benefits of loose coupling.

Evaluation of an object-oriented hardware design methodology for automotive applications

In this paper we present results in using the new object-oriented design approach OSSS (ODETTE system synthesis subset). The methodology and tools of the ODETTE (object-oriented co-design and functional test techniques) project have been developed within the context of the IST programme of the European Commission. Main focus of OSSS lies in the field of hardware design and in synthesis capability. The strategy is based on an extension of the synthesizable subset of standard systemC. The approach supports real object-oriented and synthesizable design features like classes, inheritance, templates, polymorphism and global object access. Therefore OSSS promises high efficiency in sense of capability to handle complex designs, faster development time, improved code quality and faster time to market. In contrast, standard systemC is also based on C++ constructs, but no object-oriented constructs are available yet for a synthesizable system description. We have evaluated OSSS on an automotive design example. It was chosen for the implementation of a component that is part of all video projects: A cameras exposure control unit (ExpoCU). The first main goal that was achieved is a synthesizable design by the automatic generation of an FPGA netlist from an OSSS description. Furthermore we have also proved the methodology to fulfill industrial requirements such as usability for complex system development, integration of existing IP, improved code quality and decreased development effort. Comparison will be done against existing VHDL based design flow. We especially focus on the implementation and testability by comparing the new object-oriented synthesis approach with a standard VHDL flow by laying emphasis on synthesizability. OSSS and equivalent kinds of methodology show a large potential to handle new generations of complex HW-SW systems. Moreover the gap between increasing design complexity and available methodologies already now gets bigger and bigger and thus needs to be closed by new solutions such as OSSS.

Automatic SystemC design configuration for a faster evaluation of different partitioning alternatives

In this paper we present a methodology that is based on SystemC for rapid prototyping to greatly enhance and accelerate the exploration of complex systems to optimize the system architecture. The approach introduces a methodology to automatically configure system components with regards to the memory mapping of modules. The approach reduces the implementation effort that in conventional approaches has to be done by hand to re-assign and re-configure modules in a system. This does not only save time for manual adaptation but also reduces the chance to introduce errors like known from complex manual modifications. The new approach for automatic system configuration is derived as one of the results and features that come along with the module-adapter (MA) based approach that we have proposed in different presentations (Bannow, 2004). One of the main goals, our proposed methodology has to fulfill, are industrial requirements such as applicability for complex system development, integration of existing IP, improved code quality and decreased development effort. The automated system configuration as well as the whole MA based approach greatly support the designers in the concept phase to simulate a design before the implementation starts

Enabling automated code transformation and variable tracing

To solve the challenge of hardware/software partitioning and the reuse of legacy system models (Bannow et al., 2004) introduced a module adapter (MA) based approach which is considered in section 2. The described transformation/mapping of functional code into a SystemC model still needs heavy code modifications. Besides the parser that has to be nearly as powerful as a C++ compiler the readability suffers from the necessary changes. This paper introduces an approach which reduces the code modifications to a minimum. The primary objective is to provide a solution to enable an automated application. In this novel approach, code readability and transformation effort are improved significantly by using the powerful operator overloading mechanism of C++. The presented implementation can be used to either realize transparent communication over module barriers, trace simulation data or only for debugging purposes. Some examples demonstrate the applicability and give some incitements for expedient use cases. The presented C++ code can be easily extended by inheritance for custom needs.

A Framework for Interactive Refinement of Mixed HW/SW/Analog Systems

Increasing complexity and heterogeneity leads to systems that combine the aspects of both digital hardware/software and mixed-signal embedded systems. A major difficulty is the fact that the components for mixed-signal systems are designed bottom-up, while a digital hardware/software system is designed top- down. Often this requires co-simulation, in practice involving multiple simulators from different vendors and on different platforms. Unfortunately, setting up co-simulations is a time-consuming task which is therefore done only a few times for verification purposes. In this paper we show how a plain SystemC simulation can be connected to Saber. A proxy module interfaces to the SystemC simulation and relays signals from and to Saber. A special signal synchronisation and update scheme ensures the availability of current analogue values to SystemC starting from the very beginning of each time step. Furthermore we introduce a mechanism for automatically connecting SystemC modules and show how it can be used to implement a graphical SystemC editor. A design example which compares a SystemC to Saber co-simulation to a functionally identical SystemC-AMS simulation is also included.