Christian Piguet

An On-Line Arithmetic Based FPGA for Low-Power Custom Computing

This paper describes the study of a new field programmable gate array architecture based on on-line arithmetic. This architecture, called Field Programmable On-line oPerators (FPOP), is dedicated to single chip implementation of numerical algorithms in low-power signal processing and digital control applications. FPOP is based on a reprogrammable array of on-line arithmetic operators. On-line arithmetic is a digit-serial arithmetic with most significant digits first using a redundant number system. The digit-level pipeline, the small number of communication wires between the operators and the small size of the arithmetic operators lead to high-performance parallel computations. In FPOP, the basic elements are arithmetic operators such as adders, subtracters, multipliers, dividers, square-rooters, sine or cosine operators.... An equation model is then sufficient to describe the mapping of the algorithm on the circuit. The digit-serial communication mode also significantly reduces the necessary programmable routing resources compared to standard FPGAs.

Bringing Robustness and Power Efficiency to Autonomous Energy-Harvesting Microsystems

Asynchronous circuits are well-suited to ultra-low-power design. This article presents a microsystem that is powered only by energy extracted from the environment to implement an autonomous sensing application. Key to this application is the use of asynchronous logic, which not only provides greater energy efficiency due to its event-driven nature but, more importantly, allows graceful adaptation to highly variable power availability.

Ultra-Low-Power Processor Design

Processor energy efficiency is a major issue in a majority of products; however, it is difficult to achieve it, as it is in contradiction with the main characteristic of processors, i.e. flexibility provided by embedded software. A given function implemented in random logic could consume 100–1000 times less energy than the same function implemented in a processor and corresponding embedded software. However, flexibility is more and more required, and ultra-low-power processors are mandatory. Only a few techniques have been widely used for the power consumption reduction of microcontrollers and DSP processors. This chapter will review these techniques, which are basically CPI (clocks per instruction) reduction, gated-clock mechanisms, optimal pipeline length, hardware accelerators, reconfigurable units and techniques to reduce leakage power. Several examples will be described in more details, such as some RISC 8-bit and 32-bit microcontrollers as well as some DSP cores. The latter are a good example of the necessary tradeoffs between flexibility and energy efficiency, as many random logic-based accelerators are very often used.

FPOP: field-programmable online operators

This paper describes a new digital reprogrammable architecture called Field Programmable On-line oPerators (FPOP). This architecture is a kind of FPGA dedicated to very low-power implementations of numerical algorithms in signal processing or digital control applications for embedded or portable systems. FPOP is based on a reprogrammable array of on-line arithmetic operators. On-line arithmetic is a digit-serial arithmetic with most significant digits first using a redundant number system. Because of the small size of the digit-serial operators and the small number of communication wires between the operators, single chip implementation of complex numerical algorithms can be achieved using on-line arithmetic. Furthermore, the digit-level pipeline and the small size of the arithmetic operators lead to high performance parallel computations. Compared to a standard FPGA, the basic cells in FPOP are arithmetic operators such as adders, subtracters, multipliers, dividers, square-rooters, sine or cosine operators. This granularity level allows very efficient power X delay implementations of most algorithms used in digital control and signal processing. The circuit also integrates some analog to digital and digital to analog converters.

Event-driven asynchronous voltage monitoring in energy harvesting platforms

Achieving high energy efficiency harvesting platforms requires tracking variations of the energy levels. Leveraging energy storage components whose voltage level varies with the state of charge, it becomes efficient to perform voltage monitoring. In this paper, we propose two types of analog-to-digital voltage monitoring interfaces. In both cases, their outputs directly fit asynchronous 4-phases protocol and Quasi Delay Insensitive (QDI) logic. On the one hand, in a passive voltage monitoring scheme, the platform waits for energy-events. Reacting to voltage threshold crossings, data-events are generated and sent to the asynchronous controller. On the other hand, in an active scheme, the platform waits for an asynchronous data-event before evaluating the voltage level. The analog structure is thus included into the asynchronous protocol and provides a controlled voltage monitoring. These innovative structures allow the voltage monitoring power consumption to be under 300 nA at 0.8 V and to be functional in a wide supply voltage range up to 1.8V.

Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold Designs

In this work we present a new static circuit topology for sub-threshold (sub-V T ) digital design. Proposed topology is derived from SCMOS but modifications are done to introduce new adjustable parameters to provide about 4X more control on the delay and active-mode leakage of gates. Proposed gates have full-swing input and output signaling but when the internal NMOS/PMOS transistors are off, they have negative Vgs/Vsg bias, respectively. By controlling the amount of these reverse biases, we can compensate process and temperature variations. Proposed method can be applied to any device or technology node and has 20% area and delay overheads.

Design Technologies for Nanoelectronic Systems Beyond Ultimately Scaled CMOS

As already explained in the introduction to Chap. , the development of economically feasible nanoelectronic systems requires a tight interplay between materials and fabrication technologies on the one hand and design technologies on the other. In particular, it is quite essential to explore circuit-level measures to mitigate the limitations of process variations (PVs), leakage, and reduced device reliability and, finally, to explore system-level design approaches that are better adapted to the constraints imposed by the materials, technology, and device physics. This chapter largely deals with some of these key questions that relate to design technologies for nanoelectronic systems.

Power consumption reduction in systems on Chip (SoCs)

Systems on Chip are becoming extremely complex integrated circuits, containing tens or hundreds of analog,rf and digital blocks. For most applications, they have to present extremely low power consumption. It is the case, for instance, in ad hoc networks for which 100 or 1000 SoC nodes have to sense their environment, do some processing and send by radio some information to adjacent nodes in a multi-hop fashion to reach finally a base station. The design of such SoC nodes, to achieve the required extremely low power consumption, has to performed first at the system level, including low power communication protocols and data routing through the network, node wake-up strategies, low-power software and operating systems, innovative solutions for the sensor part, flexible or reconfigurable and very low power digital processing, low-power networks on chip for the communication between embedded processors and memories, as well as low powerrf front-ends. In addition, due to the impressive technology pace, new problems have to be solved for the design of SoCs, such as the interconnect delays, reliability and the dramatic increase of the static power. Some techniques, considered as the most efficient, of dynamic as well as static power reduction are described. It is however shown that the design of SoCs in 130 nm and below will impact dramatically the design methodologies, mainly due the static power increase. Finally, if today most SoCs are powered by batteries, alternative sources of energy are reviewed.RésuméLes Systèmes sur Puce deviennent des circuits intégrés extrêmement complexes, contenant des dizaines ou des centaines de blocs analogiques, radio et numériques. Pour la majorité des applications, ils doivent présenter une consommation de puissance électrique extrêmement faible. C’est le cas, par exemple, des réseaux d’objets communicants, dans lesquels une centaine ou un millier d’objets doivent sonder leur environnement, effectuer un traitement numérique et envoyer par radio des informations à des objets voisins en plusieurs sauts vers une station de base. La conception des ces systèmes sur puce, pour parvenir à des consommations très basses, doit se faire premièrement au niveau système, considérant des protocoles de communication basse puissance et le routage des informations dans le réseau, des stratégies de réveil des objets communicants, des logiciels et des systèmes d’exploitation basse puissance, des solutions innovatrices pour les capteurs, des processeurs de traitement numérique à la fois flexibles, reconfigurables et basse puissance, des réseaux de communication entre processeurs et mémoires embarqués, ainsi que des têtes radiofréquences à très basse puissance. De plus, les progrès technologiques impressionnants ont pour résultat de poser des nouveaux problèmes dans la conception des systèmes sur puce, comme les délais des interconnexions, la fiabilité et l’accroissement significatif de la puissance statique. Quelques techniques parmi les plus efficaces de réduction des puissances dynamique et statique sont présentées. Cependant, la conception des systèmes sur puce dans des technologies de 130 nanomètres et plus bas va remettre en cause les méthodes de conception habituelles, essentiellement à la suite de l’accroissement significatif de la puissance statique. Finalement, si la majorité des systèmes sur puce d’aujourd’hui sont alimentés par des batteries, des sources d’énergies alternatives sont décrites.