Christian Spagnol

Energy-Efficient Low Duty Cycle MAC Protocol for Wireless Body Area Networks

This paper presents an energy-efficient medium access control protocol suitable for communication in a wireless body area network for remote monitoring of physiological signals such as EEG and ECG. The protocol takes advantage of the static nature of the body area network to implement the effective time-division multiple access (TDMA) strategy with very little amount of overhead and almost no idle listening (by static, we refer to the fixed topology of the network investigated). The main goal is to develop energy-efficient and reliable communication protocol to support streaming of large amount of data. TDMA synchronization problems are discussed and solutions are presented. Equations for duty cycle calculation are also derived for power consumption and battery life predictions. The power consumption model was also validated through measurements. Our results show that the protocol is energy efficient for streaming communication as well as sending short bursts of data, and thus can be used for different types of physiological signals with different sample rates. The protocol is implemented on the analog devices ADF7020 RF transceivers.

Energy-Efficient TDMA-Based MAC Protocol for Wireless Body Area Networks

Body Area Networks (BAN) are a specific type of Network structure. They are spread over a very small area and their available power is heavily constrained. Hence it is useful to have gateway points in the network, such as nodes carried around the belt, that are less power constrained and can be used for network coordination. This network structure can result in very low transmission power/range for the sensors and effective TDMA timing control. This paper presents an energy-efficient MAC protocol for communication within the Wireless Body Area Network. The protocol takes advantage of the fixed nature of the Body Area Network to implement a TDMA strategy with very little communication overhead, long sleep times for the sensor transceivers and robustness to communication errors. The protocol is implemented on the Analog Devices ADF7020 RF transceivers.

Hardware Implementation of

Low density parity check (LDPC) codes over GF(2m) are an extension of binary LDPC codes with significantly higher performance. However, the computational complexity of the encoders/decoders for these codes is also higher. Hence there is a substantial lack of hardware implementations for LDPC over GF(2m) codes. This paper proposes a novel variation of the belief propagation algorithm for GF(2m) LDPC codes. The new algorithm results in a reduced hardware complexity when implemented in VLSI. The serial architecture of the novel decoding algorithm and two other algorithms for LDPC over GF(2m) are implemented on an FPGA. The results show that the proposed algorithm has substantial advantages over existing methods. We show that the implementation of LDPC over GF(2m) decoder is feasible for short to medium length codes. The additional complexity of the decoder is balanced by the superior performance of GF(2m) LDPC codes.

{\rm GF}(2^{m})

Low Density Parity Check (LDPC) codes over GF(2m) are an extension of binary LDPC codes that have not been studied extensively. Performances of GF(2m) LDPC codes have been shown to be higher than binary LDPC codes, but the complexity of the encoders/decoders increases. Hence there iS a substantial lack of hardware implementations for LDPC over GF(2m) codes. This paper presents a FPGA serial implementation of two decoding algorithms for LDPC over GF(2m). The results prove that the implementation of LDPC over GF(2m) decoding is feasible and the extra complexity of the decoder is balanced by the superior performance of GF(2m) LDPC codes.

LDPC Decoders

Ubiquitous vital signs sensing and processing are promising alternatives to conventional clinical and ambulatory healthcare. Novel sensors, low power solutions for processing and wireless connectivity are creating new opportunities for wearable devices which allow continuous and long term monitoring, while maintaining freedom of movement for the users. This paper presents a low-power embedded platform with novel high sensitivity electric potential dry surface sensors that can be used in either contact or non-contact mode to measure biomedical signals. The proposed low power system is optimized to compute the heart rate and respiratory rate close to the sensors. This approach reduces the amount of data that needs to be transmitted to a host device. It allows also the platform to be autonomous and wearable or even be used in cars for applications such as driver drowsiness detection. Experimental measurements show the acquisition and the processing of data from sensors and the low power consumption achieved with the node in different modes of operation.

FPGA Implementations of LDPC over GF(2 m ) Decoders

Nowadays, the technology advancements of sensors, low power mixed-signal/RF circuits, wireless communication and Wireless Sensor Networks (WSNs) have enabled the design of compact, low power, high performance and low cost solutions for a wide range of applications, surveillance, building monitoring, sports/fitness, and of particular interesting are applications for health care. Novel sensors for human biomedical signal together with wireless connectivity and low power solutions are creating new opportunities for wearable devices which allow continuous monitoring together with freedom of movement of the users. This paper presents a low-power wearable sensor networks platform for on-body physiological measurements and wireless data communications. The platform hosts novel high sensitivity electric potential dry surface sensors that can be used in either contact or non-contact mode to measure ECG and EMG signals. Heart rate and respiration rate is performed runtime directly on the node. This approach reduces the amount of data than need to be transmitted, from raw measurement to analyzed data. In doing so the duty cycle of the radio has been reduced and the power consumption of the node optimized. Experimental measurements show the acquisition and processing of data from sensors and the low power consumption achieved with the node in different modalities.

A low power wireless node for contact and contactless heart monitoring

With the advent of deep submicron CMOS technology, process parameter statistical variations are increasing resulting in unpredictable device behaviour. The issue is even aggravated by low power requirements which are stretching transistor operation into near/sub threshold regime. Consequently, traditional delay models fail to accurately capture the circuit behaviour. In view of this we introduce an Inverse Gaussian Distribution (IGD) based delay model, which accurately captures the delay distribution under process variations at ultra low, near or below threshold, power supply values. We demonstrate that the IGD model captures the transistor delay distribution with a greater accuracy than the traditional Gaussian one. Moreover it exhibits linear compositionality such that the key model parameters can be straightforward propagated form device/gate level to circuit level. Our simulations indicate that, when compared with Monte Carlo SPICE simulation results, it provides high accuracy, e.g., an average error less than 0.8%, 1.2%, and 1.7% for Majority Voter, XOR gate, and 16-bit Ripple Carry Adder, respectively, while providing orders of magnitude simulation time reductions.

Wearable low power dry surface wireless sensor node for healthcare monitoring application

In multi-hop wireless sensor networks (WSN), the data transmitted from sensor nodes is highly susceptible to error corruption introduced by noisy channels. It is important to use some error correction schemes in order to control the errors introduced and to reduce the number of automatic requests for retransmission. The sensor nodes are typically wireless nodes with limited storage and computational power. Thus the error control schemes should be energy efficient at sensor nodes level. Most of the reported works assume that both encoding and decoding are performed at every node. The idea of this paper is to perform encoding only at the first node and decoding will be done at the base station. We assume that the base station has enough power to run complex decoding algorithms. This paper provides a model for energy consumed and the probability of receiving a correct word for multi-hop WSN at base station when considering a number of coding schemes and hops. The emphasis is on using powerful codes with low complexity encoding. Several powerful codes like Reed-Solomon (RS), list decoded RS codes, multivariate interpolation decoded RS codes (MIDRS) and Hermitian codes are investigated for this scheme. All these codes have very simple encoding based on RS type encoders and we will show that this scheme consumes less power than reported schemes while maintaining a low probability of error.

Linear Compositional Delay Model for the Timing Analysis of Sub-Powered Combinational Circuits

In this paper, several implementations of the recently introduced PGDBF decoder for LDPC codes are proposed. In [2], the authors show that using randomness in bit-flipping decoders can greatly improve the error correction performance. In this paper, two models of random generators are proposed and compared through hardware implementation and performance simulation. A conventional implementation of the random generator through LFSR as a first design, and a new approach using binary sequences that are produced by the LDPC decoder, named IVRG, as second design. We show that both implementation of the PGDBF improve greatly the error correction performance, while maintaining the same large throughtput. However, the performance gain requires a large hardware overhead in the case of LFSR-PGDBF, while the overhead is limited to only 10% in the case of the IVRG-PGDBF.

Analysis of a set of error correcting schemes in multi-hop wireless sensor networks

This paper describes an FPGA implementation of a decoder for a particular family of low density parity check (LDPC) codes, the quasi-cyclic LDPC codes. The structure of a quasi-cyclic code is well known and allows us to reduce the complexity of the interconnections between bit nodes and check nodes. The decoder has a semi-parallel architecture and it takes full advantage of the structure of the code and the hardware resources present in an FPGA. We achieve simple memory controller resulting in an efficient use of the memory. The decoder is implemented based on the parameters that characterize a quasi-cyclic LDPC code. This makes it easily adaptable for a class of quasi-cyclic codes. We evaluate the performance of our codes and present some FPGA design trade-off.