William P. Marnane

Energy-Efficient Low Duty Cycle MAC Protocol for Wireless Body Area Networks

This paper presents an energy-efficient medium access control protocol suitable for communication in a wireless body area network for remote monitoring of physiological signals such as EEG and ECG. The protocol takes advantage of the static nature of the body area network to implement the effective time-division multiple access (TDMA) strategy with very little amount of overhead and almost no idle listening (by static, we refer to the fixed topology of the network investigated). The main goal is to develop energy-efficient and reliable communication protocol to support streaming of large amount of data. TDMA synchronization problems are discussed and solutions are presented. Equations for duty cycle calculation are also derived for power consumption and battery life predictions. The power consumption model was also validated through measurements. Our results show that the protocol is energy efficient for streaming communication as well as sending short bursts of data, and thus can be used for different types of physiological signals with different sample rates. The protocol is implemented on the analog devices ADF7020 RF transceivers.

EEG-based neonatal seizure detection with Support Vector Machines.

Objective The study presents a multi-channel patient-independent neonatal seizure detection system based on the Support Vector Machine (SVM) classifier. Methods A machine learning algorithm (SVM) is used as a classifier to discriminate between seizure and non-seizure EEG epochs. Two post-processing steps are proposed to increase both the temporal precision and the robustness of the system. The resulting system is validated on a large clinical dataset of 267 h of EEG data from 17 full-term newborns with seizures. Results The performance of the system using event-based metrics is reported. The system showed the best up-to-date performance of a neonatal seizure detection system. The system was able to achieve an average good detection rate of ∼89% with one false seizure detection per hour, ∼96% with two false detections per hour, or ∼100% with four false detections per hour. An analysis of errors revealed sources of misclassification in terms of both missed seizures and false detections. Conclusions The results obtained with the proposed SVM-based seizure detection system allow for its practical application in neonatal intensive care units. Significance The proposed SVM-based seizure detection system can greatly assist clinical staff, in a neonatal intensive care unit, to interpret the EEG. The system allows control of the final decision by choosing different confidence levels which makes it flexible for clinical needs. The obtained results may provide a reference for future seizure detection systems.

A comparison of quantitative EEG features for neonatal seizure detection

OBJECTIVE This study was undertaken to identify the best performing quantitative EEG features for neonatal seizures detection from a test set of 21. METHODS Each feature was evaluated on 1-min, artefact-free segments of seizure and non-seizure neonatal EEG recordings. The potential utility of each feature for neonatal seizure detection was determined using receiver operating characteristic analysis and repeated measures t-tests. A performance estimate of the feature set was obtained using a cross-fold validation and combining all features together into a linear discriminant classifier model. RESULTS Significant differences between seizure and non-seizure segments were found in 19 features for 17 patients. The best performing features for this application were the RMS amplitude, the line length and the number of local maxima and minima. An estimate of the patient independent classifier performance yielded a sensitivity of 81.08% and specificity of 82.23%. CONCLUSIONS The individual performances of 21 quantitative EEG features in detecting electrographic seizure in the neonate were compared and numerically quantified. Combining all features together into a classifier model led to superior performance than that provided by any individual feature taken alone. SIGNIFICANCE The results documented in this study may provide a reference for the optimum quantitative EEG features to use in developing and enhancing neonatal seizure detection algorithms.

Efficient architectures for implementing montgomery modular multiplication and RSA modular exponentiation on reconfigurable logic

This paper presents a review of some existing architectures for the implementation of Montgomery modular multiplication and exponentiation on FPGA (Field Programmable Gate Array). Some new architectures are presented, including a pipelined architecture exploiting the maximum carry chain length of the FPGA which is used to implement the modular exponentiation operation required for RSA encryption and decryption. Speed and area comparisons are performed on the optimised designs. The issues of targeting a design specifically for a reconfigurable device are considered, taking into account the underlying architecture imposed by the target technology.

Optimisation of the SHA-2 family of hash functions on FPGAs

Hash functions play an important role in modern cryptography. This paper investigates optimisation techniques that have recently been proposed in the literature. A new VLSI architecture for the SHA-256 and SHA-512 hash functions is presented, which combines two popular hardware optimisation techniques, namely pipelining and unrolling. The SHA processors are developed for implementation on FPGAs, thereby allowing rapid prototyping of several designs. Speed/area results from these processors are analysed and are shown to compare favourably with other FPGA-based implementations, achieving the fastest data throughputs in the literature to date

FPGA Implementations of the Round Two SHA-3 Candidates

The second round of the NIST-run public competition is underway to find a new hash algorithm(s) for inclusion in the NIST Secure Hash Standard (SHA-3). This paper presents the full implementations of all of the second round candidates in hardware with all of their variants. In order to determine their computational efficiency, an important aspect in NISTs round two evaluation criteria, this paper gives an area/speed comparison of each design both with and without a hardware interface, thereby giving an overall impression of their performance in resource constrained and resource abundant environments. The implementation results are provided for a Virtex-5 FPGA device. The efficiency of the architectures for the hash functions are compared in terms of throughput per unit area.

An FPGA implementation of a GF(p) ALU for encryption processors

Abstract Secure electronic and internet transactions require public key cryptosystems to establish and distribute shared secret information for use in the bulk encryption of data. For security reasons, key sizes are in the region of hundreds of bits. This makes cryptographic procedures slow in software. Hardware accelerators can perform the computationally intensive operations far quicker. Field-Programmable Gate Arrays are well-suited for this application due to their reconfigurability and versatility. Elliptic Curve Cryptosystems over GF( p ) have received very little attention to date due to the seemingly more attractive finite field GF(2 m ). However, we present a GF( p ) Arithmetic Logic Unit which can perform 160-bit arithmetic at clock speeds of up to 50 MHz.

Performance assessment for EEG-based neonatal seizure detectors

Objective This study discusses an appropriate framework to measure system performance for the task of neonatal seizure detection using EEG. The framework is used to present an extended overview of a multi-channel patient-independent neonatal seizure detection system based on the Support Vector Machine (SVM) classifier. Methods The appropriate framework for performance assessment of neonatal seizure detectors is discussed in terms of metrics, experimental setups, and testing protocols. The neonatal seizure detection system is evaluated in this framework. Several epoch-based and event-based metrics are calculated and curves of performance are reported. A new metric to measure the average duration of a false detection is proposed to accompany the event-based metrics. A machine learning algorithm (SVM) is used as a classifier to discriminate between seizure and non-seizure EEG epochs. Two post-processing steps proposed to increase temporal precision and robustness of the system are investigated and their influence on various metrics is shown. The resulting system is validated on a large clinical dataset of 267 h. Results In this paper, it is shown how a complete set of metrics and a specific testing protocol are necessary to extensively describe neonatal seizure detection systems, objectively assess their performance and enable comparison with existing alternatives. The developed system currently represents the best published performance to date with an ROC area of 96.3%. The sensitivity and specificity were ∼90% at the equal error rate point. The system was able to achieve an average good detection rate of ∼89% at a cost of 1 false detection per hour with an average false detection duration of 2.7 min. Conclusions It is shown that to accurately assess the performance of EEG-based neonatal seizure detectors and to facilitate comparison with existing alternatives, several metrics should be reported and a specific testing protocol should be followed. It is also shown that reporting only event-based metrics can be misleading as they do not always reflect the true performance of the system. Significance This is the first study to present a thorough method for performance assessment of EEG-based seizure detection systems. The evaluated SVM-based seizure detection system can greatly assist clinical staff, in a neonatal intensive care unit, to interpret the EEG.

Efficient hardware for the tate pairing calculation in characteristic three

In this paper the benefits of implementation of the Tate pairing computation on dedicated hardware are discussed. The main observation lies in the fact that arithmetic architectures in the extension field GF(36m) are good candidates for parallelization, leading to a similar calculation time in hardware as for operations over the base field GF(3m). Using this approach, an architecture for the hardware implementation of the Tate pairing calculation based on a modified Duursma-Lee algorithm is proposed.

Hardware Implementation of

Low density parity check (LDPC) codes over GF(2m) are an extension of binary LDPC codes with significantly higher performance. However, the computational complexity of the encoders/decoders for these codes is also higher. Hence there is a substantial lack of hardware implementations for LDPC over GF(2m) codes. This paper proposes a novel variation of the belief propagation algorithm for GF(2m) LDPC codes. The new algorithm results in a reduced hardware complexity when implemented in VLSI. The serial architecture of the novel decoding algorithm and two other algorithms for LDPC over GF(2m) are implemented on an FPGA. The results show that the proposed algorithm has substantial advantages over existing methods. We show that the implementation of LDPC over GF(2m) decoder is feasible for short to medium length codes. The additional complexity of the decoder is balanced by the superior performance of GF(2m) LDPC codes.