Christian Stangier

Speeding Up Image Computation by Using RTL Information

Image computation is the core operation for optimization and formal verification of sequential systems like controllers or protocols. State exploration techniques based on OBDDs use a partitioned representation of the transition relation to keep the OBDD-sizes manageable. This paper presents a new approach that significantly increases the quality of the partitioning of the transition relation of controllers given in the hardware description language Verilog. The heuristic has been successfully applied to reachability analysis and symbolic model checking of real life designs, resulting in a significant reduction both in CPU time and memory consumption.

Hierarchical image computation with dynamic conjunction scheduling

Image computation is the core operation for optimization and formal verification of sequential systems like controllers or protocols. State exploration techniques based on ordered binary decision diagrams (OBDDs) use a partitioned representation of the transition relation to keep the OBDD-sizes manageable. This paper presents algorithms for building a hierarchically partitioned transition relation and conjunction scheduling based on this partitioning. The conjunction scheduling algorithm allows one to dynamically reorder partitions and is targeted to improve the AndExist operation. Model checking experiments prove the effectiveness of the new algorithms.

Speeding up symbolic model checking by accelerating dynamic variable reordering

Symbolic Model checking is a widely used technique in sequential verification. As the size of the OBDDs and also the computation time depends on the order of the input variables, the verification may only succeed if a well suited variable order is chosen. Since the characteristics of the represented functions are changing, the variable order has to be adapted dynamically. Unfortunately, dynamic reordering strategies are often very time consuming and sometimes do not provide any improvement of the OBDD representation. This paper presents adaptions of reordering techniques originally intended for combinatorial verification to the specific requirements of symbolic model checking. The techniques are orthogonal in the way that they use either structural information about the OBDDs or semantical information about the represented functions. The application of these techniques substantially accelerates the reordering process and makes it possible to finish computations, that are too time consuming, otherwise.

A new partitioning scheme for improvement of image computation

Image computation is the core operation for optimization and formal verification of sequential systems like controllers or protocols. State exploration techniques based on OBDDs use a partitioned representation of the transition relation to keep the OBDD-sizes manageable. This paper presents a new approach that significantly increases the quality of the partitioning of the transition relation of finite state machines. The heuristic has been successfully applied to reachability analysis and symbolic model checking of real life designs, resulting in a significant reduction in CPU time as well as in memory consumption.

Increasing efficiency of symbolic model checking by accelerating dynamic variable reordering

Model checking has been proven to be a powerful tool in verification of sequential circuits, reactive systems, protocols, etc. The model checking of systems with huge state spaces is possible only if there is a very efficient representation of the model. Ordered Binary Decision Diagrams (OBDDs) allow an efficient symbolic representation of the model. Our goal is to accelerate the variable reordering process but retaining good OBDD sizes. To obtain this, we adapted two methods introduced by Meinel and Slobodova called Block Restricted Sifting (BRS) and Sample Sifting to the needs of model checking.

Algorithms and heuristics in VLSI design

But it turned out that all optimization problems needed for OBDDs to work efficiently are at least NP-hard. For some problems it is shown that even approximation schemes do not exist. Thus, only heuristic approaches remain applicable. We will present heuristic approaches to some basic problems in OBDD based formal verification, i.e., variable reordering and partitioning of transition relations. Since we apply our heuristics to intractable optimization problems the quality of the approach can only be judged by the use of benchmarks. We will discuss the benchmarking problems for OBDD applications. A meaningful evaluation of heuristic algorithms requires a suited experimentation environment. We will discuss issues as use of open source software and the influence of parameter settings. This article is structured as followed. The next section gives basic definitions of OBDDs, their algorithms and explains the most important applications, where OBDDs are used. In Section 7.3 we will present and improved heuristic for the variable reordering Problem. In Section 7.4 we will give algorithms for a typical OBDD-based application, namely the partitioning of transition relations.

Data structures for Boolean functions BDDs: Foundations and applications

This article gives an outline of a lecture about ordered binary decision diagrams (OBDDs). Introduced in 1986, OBDDs nowadays are the state-of-the-art data structure for representation of Boolean functions in electronic design automation (EDA).