Christian Steger

Automated Power Characterization for Run-Time Power Emulation of SoC Designs

With the advent of increasingly complex systems, the use of traditional power estimation approaches is rendered infeasible due to extensive simulation times. Hardware accelerated power emulation techniques, performing power estimation as a by-product of functional emulation, are a promising solution to this problem. However, only little attention has been awarded so far to the problem of devising a generic methodology capable of automatically enabling the power emulation of a given system-under-test. In this paper, we propose an automated power characterization and modeling methodology for high level power emulation. Our methodology automatically extracts relevant model parameters from training set data and generates an according power model. Furthermore, we investigate the automation of the power model hardware implementation and the automated integration into the overall system’s HDL description. For a smart card controller test-system the automatically created power model reduces the average estimation error from 11.78% to 4.71% as compared to a manually optimized one.

A UHF RFID measurement and evaluation test system

SummaryUHF RFID tags have demonstrated considerable degradation of performance when being attached to products. Absorption, reflection, detuning, and other RF effects decrease the sensitivity of the tags. We are presenting an UHF RFID measurement and performance evaluation test system, which allows for evaluations of designs of labels and ICs. Furthermore, it provides means for quantifying tag performance in various applications through measurements and tests.ZusammenfassungUHF RFID Tags zeigen eine beachtliche Verschlechterung der Leistung, sobald sie an Objekten angebracht werden. Absorption, Reflexion, Verstimmung und andere RF-Effekte vermindern die Transponder-Sensitivität. Es wird ein UHF RFID-Mess- und Leistungsevaluationstestsystem vorgestellt, welches bei der Evaluierung von Labeldesigns und ICs zur Anwendung kommt.

An emulation-based real-time power profiling unit for embedded software

The power consumption of battery-powered and energy-scavenging devices has become a major design metric for embedded systems. Increasingly complex software applications as well as rising demands in operating times while having restricted power budgets make power-aware system design indispensable. In this paper we present an emulation-based power profiling approach allowing for real-time power analysis of embedded systems. Power saving potential as well as power-critical events can be identified in much less time compared to power simulations. Hence, the designer can take countermeasures already in early design stages, which enhances development efficiency and decreases time-to-market. Accuracies achieved for a deep submicron smart-card controller are greater than 90% compared to gate-level simulations.

Simulation based verification of energy storage architectures for higher class tags supported by energy harvesting devices

Abstract Enhanced RFID tag technology especially in the UHF frequency range provides an extended functionality like high operating range and sensing and monitoring capabilities. Such complex functionality requires extended system structures including data acquisition units, real time clocks and active transmitters that cause a high energy consumption of the tag and require an on-board energy store (battery). Since the lifetime is a key parameter for the reliability of an RFID system, the energy budget of the higher class tag has to be as balanced as possible. This can be achieved by using energy harvesting devices as additional power supplies. The PowerTag 1 project and thus this paper propose special energy storage structures, which interface energy harvesting devices and deal with their special requirements to be used with battery-driven higher class UHF RFID tags. Different implementation variants of such structures are compared by using accurate simulation models of various parts of the system. The results of the simulation are compared to provided manufacturer performance parameters of a state-of-the-art higher class UHF RFID system.

Automatic and optimal allocation of safety integrity levels

Powertrain electrification of vehicles leads to a higher number of sensors, actuators and control functions resulting in increasing complexity. Due to the safety-criticality of the functionalities, safety standards must be considered during system development. The safety standard ISO 26262 defines discrete ASILs (Automotive Safety Integrity Levels) that must be identified and allocated to the components of the system under development. Once allocated, they determine the applicable requirements of ISO 26262 and the necessary safety measures to accordingly minimize residual risk. Fu rthermore, the allocated ASILs directly influence the development efforts and the costs per piece of the system components. Manual elaboration of an ASIL allocation that is economic and assures functional safety is complex and cumbersome. This work presents a method that allows the automatic allocation of ASILs to the system components. In our approach ASIL allocation is interpreted as an ILP (Integer Linear Programming) problem. This allows obtaining an ASIL allocation that is optimal with respect to an objective function that is subject to constraints. These constraints are derived from the results of PHA (Preliminary Hazard Analysis), FTA (Fault Tree Analysis) and preferences of the safety engineer. The approach is evaluated by the case study of hybrid electric vehicle development.

A side channel attack countermeasure using system-on-chip power profile scrambling

Since the discovery that hardware used for cryptographic applications could leak secret information through its power or radiation profile a wide range of possible attack methods has been published. The rapid evolution of these side-channel attacks made it increasingly important to minimize this possible information leakage. Additionally timing information also derived from this power profile is used to control fault-attack campaigns to drive the system into an unintended state. Therefore a wide range of leakage countermeasures has been developed for dedicated cryptographic hardware. Contrariwise only little work is available concerning power profile scrambling techniques for cryptographic software implementations running on general purpose architectures. Such implementations often include power management hardware to cope with several power budget constraints which could be used to influence the systems power consumption during run-time. This paper proposes a novel side channel attack countermeasure technique using such power management methods in combination with techniques for power profile manipulation. State-of-the-art power estimation hardware using a reduced power model allows for the efficient on-line monitoring and manipulation of the power consumption and radiation profile.

Accelerating early design phase differential power analysis using power emulation techniques

The personal banking and ID sector has seen a tremendous change in recent years, partially caused by the widespread introduction of smart-cards. Because of the extensive implications of a successful attack on these devices, a wide range of practical as well as purely academic attacks has been developed during the last years. These attacks have unveiled weaknesses in hardware as well as software implementations of several different, partially widely used cryptographic algorithms. An especially powerful method, the differential power analysis (DPA), extracts secret information from power consumption and electro-magnetic emission profiles. The efficiency of a DPA attack significantly depends on the quality of the cryptographic algorithm implementation. These traces currently can only be generated using real hardware or simulation-based approaches. Depending on the chosen simulation accuracy these evaluations result in time-consuming RTL and SPICE simulations often limiting the maximum amount of available execution traces. This paper introduces a novel high-speed methodology for early security evaluations of integrated processor systems using power emulation. First, the usage of power emulation hardware allows for the estimation of attack effort that an adversary will have to invest to gain secret information from an algorithms execution profile. Second, countermeasures against differential power analysis attacks can be quickly evaluated in terms of effectiveness. The shown approach uses semi-automatic characterization techniques and fully synthesizable emulation hardware to reduce the designers dependency on time-consuming simulation runs.

A measurement platform for energy harvesting and software characterization in WSNs

Wireless Sensor Network (WSN) nodes are resource- constrained computing devices. Adaptive behavior of autonomously working WSNs tries to maximize the cost efficiency of deployments. This includes maximizing the lifetime through power consumption optimization and recharging energy reservoirs with the use of energy harvesting. The adaptive behavior that leads to efficient resource usage needs information about the WSNs energy balance for decision making. We present a novel platform to measure the harvested, stored and dissipated energy. For being applicable to different environments it allows to attach different energy harvesting devices (EHDs). EHDs do not provide power continuously. Power availability patterns are used to determine how these sources can be used efficiently. Models from harvesting theory try to adapt to it. We implement a model that targets energy neutrality on our platform. It is used to evaluate the model and improve it. Our novel platform can be used to evaluate theories that model different sources. It can utilize and characterize thermoelectric, piezoelectric and magnetic induction generators and solar cells. The measurement platform tracks energy dissipation too. Mote software is implemented to establish communication to the platform. A sample application on top of it shows that the system can be used for software characterization. This paper contributes a novel modular and low-power design for measurement platforms for WSNs. It shows utilization of different energy sources and the ability to supply different mote types. Our work shows how theories for energy harvesting can be evaluated and improved. Our work also contributes to the field of simulation and emulation through online software characterization. The approach improves in accuracy and completeness over the capabilities of offline simulation.

A Computer-Aided Approach to Preliminary Hazard Analysis for Automotive Embedded Systems

Powertrain electrification of automobiles leads to a higher number of sensors, actuators and control functions, which in turn increases the complexity of automotive embedded systems. The safety-criticality of the system requires the application of Preliminary Hazard Analysis early in the development process. This is a necessary first step for the development of an automotive embedded system that is acceptably safe. Goal of this activity is the identification and classification of hazards and the definition of top level safety requirements that are the basis for designing a safety-critical embedded system that is able to control or mitigate the identified hazards. A computeraided framework to support Preliminary Hazard Analysis for automotive embedded systems is presented in this work. The contribution consists of (1) an enhancement for Preliminary Hazard Analysis to the domain-specific language EAST-ADL, as well as (2) the identification of properties that indicate the correct application of Preliminary Hazard Analysis using the language. These properties and an analysis model reflecting the results of the Preliminary Hazard Analysis are used for the automated detection of an erroneously applied Preliminary Hazard Analysis (property checker) and the automated suggestion and application of corrective measures (model corrector). The applicability of the approach is evaluated by the case study of hybrid electric vehicle development.

Automatic Test Generation From Semi-formal Specifications for Functional Verification of System-on-Chip Designs

In common design flows of system-on-chip (SoC) designs functional verification requires 70% of the entire design effort. Most of the effort for functional verification is spent on finding and creating adequate testcases to verify that the modeled design corresponds to its specification. This is done manually, since automatic test case generation from the specification is often not possible due to the informal, non-machine readable structure of the specification document. Formal specification languages would ease the parsing process, however, these formats are difficult to use by system engineers from different domains. A promising trade-off are semi-formal specification formats, which are both easy-to-parse and easy-to-use. The SIMBA project focuses on semi-formal use case-based specification formats, which are used to automatically generate a transaction-based SystemC verification platform. Finally, these SystemC testcases are simulated together with the System-under- Verification (SuV) to verify that it fulfills the given specification. This results in a novel design methodology regarding requirements elicitation and automatic test case generation. A demonstration is given by applying this methodology to a SystemC RFID controller model. It is shown that the demonstrated approach automates and improves the functional verification of SoCs.