Christianto C. Liu

Bridging the processor-memory performance gap with 3D IC technology

Microprocessor performance has been improving at roughly 60% per year. Memory access times, however, have improved by less than 10% per year. The resulting gap between logic and memory performance has forced microprocessor designs toward complex and power-hungry architectures that support out-of-order and speculative execution. Moreover, processors have been designed with increasingly large cache hierarchies to hide main memory latency. This article examines how 3D IC technology can improve interactions between the processor and memory. Our work examines the performance of a single-core, single-threaded processor under representative work loads. We have shown that reducing memory latency by bringing main memory on chip gives us near-perfect performance. Three-dimensional IC technology can provide the much needed bandwidth without the cost, design complexity, and power issues associated with a large number of off-chip pins. The principal challenge remains the demonstration of a highly manufacturable 3D IC technology with high yield and low cost.

Three-dimensional integration: technology, use, and issues for mixed-signal applications

Three-dimensional (3-D) integration provides opportunities in large-scale integration of mixed-signal and general system-on-chip applications with improved performance, through increased density and mixing of different active and passive technologies. This paper reports a novel low-thermal-budget 3-D fabrication technique-multilayers with buried structures (MLBS) and an analysis of its applicability to mixed-signal integration. The MLBS technique uses a low temperature of 450/spl deg/C to transfer a single-crystal silicon layer over a processed wafer consisting of buried in-plane and out-of-plane interconnects obtained through a dual Damascene process. Devices can continue to be processed on this transferred layer. Electrical characteristics of MOS capacitors (D/sub it/=4.7/spl times/10/sup 10/ cm/sup -2/ eV/sup -1/) and 3-D integrated planar CMOS transistors (3-D CMOS), fabricated using MLBS, are consistent with integration requirements. Our analog analysis includes an investigation of thermal effects important to analog applications with continuous operation of transistors in forward active bias, as well as of the coupling isolation derived from use of a ground-plane. Use of high density local interconnectivity improves the thermal properties of 3-D CMOS over that of silicon-on-insulator, and use of a ground plane is shown to lead to an improvement of better than 8 dB in coupling isolation.

Multi-layers with buried structures (MLBS): an approach to three-dimensional integration

A new multi-layers with buried structures (MLBS) approach that is suitable for three-dimensional integration is described. The silicon layering technique uses temperatures as low as 450 C, comparable to some of the steps in back-end-of-line processing of CMOS and provides a solution to temperature constraints in integration.

Mapping system-on-chip designs from 2-D to 3-D ICs

System-on-chip (SoC) designs suffer from the growing global interconnect delay as device density and chip area increase. Three-dimensional integrated circuits (3D ICs) have been proposed as a way to reduce global wire length. Despite this key advantage of 3D ICs, 3D designs must effectively address two critical issues: heat dissipation and manufacturing cost. In this paper, we propose a new methodology that explores the trade-off between performance and cost of a SoC design, while keeping maximum on-chip temperature at an acceptable level. We analyze the performance of two multimedia systems and describe the implications of scaling SoC designs to 3D.

Crosstalk reduction in mixed-signal 3-D integrated circuits with interdevice layer ground planes

We show nearly 8 dB of crosstalk reduction using ground planes between active device layers in three-dimensional (3-D) integrated circuits. Our experimental work utilizes two planes of MOS transistors with tungsten or polysilicon ground planes designed to attenuate crosstalk. Theoretical simulations, using an electromagnetic solver, and the experimental results are consistent with analytical results. The key result verified is that a ground plane, whose footprint shadows the device area, is sufficiently large for effective attenuation. The interdevice layer ground plane provides an effective means to achieve crosstalk reduction in 3-D mixed-signal/RF integration because of simple fabrication and high coupling isolation.

Crosstalk attenuation with ground plane structures in three-dimensionally integrated mixed signal systems

We report significant crosstalk reduction between two transistor planes in 3D integrated circuits (3D ICs) using tungsten ground plane structures as the isolation layer. Simulation and experimental results show /spl sim/8 dB of crosstalk attenuation. A significant conclusion of our study is that a ground plane that physically shadows the region it is isolating is optimum for deriving most of the benefits of isolation. We also show that for ground planes composed of standard MOS metallizations, i.e. W, Al, Cu, similar crosstalk isolation is expected. The inter-device ground plane structures have potential to be standard isolation technology for 3D mixed-signal and RF integrated systems due to simple fabrication and significant crosstalk attenuation.

Electronics at Nanoscale: Fundamental and Practical Challenges, and Emerging Directions

In electronics, i.e. when using charge transport and change of electromagnetic fields in devices and systems, non-linearity, collective effects, and a hierarchy of design across length and time scales is central to efficient information processing through manipulation and transmission of bits. Silicon-based electronics brings together a systematic interdependent framework that connects software and hardware to reproducibility, speed, power, noise margin, reliability, signal restoration and communication, low defect count, and an ability to do predictive design across the scales. In the limits of nanometer scale, the dominant practical constraints arise from power dissipation in ever smaller volumes and of efficient signal interconnectivity commensurate with the large density of devices. These limitations are tied to the physical basis in charge transport and changes of fields, and equally apply to other materials – hard, soft or molecular. At the largest scale, the limitations arise from partitioning and hierarchical apportionment for system performance, ease of design and manufacturing. Power management, behavioral encapsulation, fault tolerance, congestion avoidance, timing, placement, routing, electromagnetic cross-talk, etc. all need to be addressed from the perspective of centimeter scale. We take a hierarchical view of the underlying fundamental and practical challenges of the conventional and unconventional approaches using the analytic framework appropriate to the length scale to distinguish between fact and fantasy, and to point to practical emerging directions with a system-scale perspective.

Three-dimensional integration in silicon electronics

As silicon electronics reaches length scales of 100 to 10 nm, device densities of 10/sup 9/ to 10/sup 11/ cm/sup -2/, interconnect densities of 10/sup 10/ to 10/sup 12/ cm/sup -2/, and applications across the spectrum of digital, analog, and mixed-signal domain, a number of key issues arise related to maintaining the improvement in performance, cost, power, and designability. Three-dimensional integration incorporating planar transistors offers interesting new directions for continuing improvements. Adaptive modifications of the planar transistors offer higher scalability and functionality, higher vertical interconnectivity in between device planes can reduce interconnect delays, higher programmability using configurable elements can provide efficient signal and energy flow, higher digital-analog isolation using ground-planes can provide cross-talk improvements for mixed-signal applications, and a power-aware design can allow control of temperature and power dissipation.

Performance advantages of 3-D digital integrated circuits in a mixed SOI and bulk CMOS design space

Three-dimensional (3-D) integrated circuits (ICs), with multiple stacked device layers, offer a unique design opportunity to use both bulk and partially depleted (PD) silicon-on-insulator (SOI) CMOS devices in a single circuit design. Such 3-D designs can, for example, minimize the body effect common in bulk designs and reduce adverse floating-body effects (FBE) common in PD SOI designs. Sequential 3-D technology such as exfoliation-based single-crystal silicon layer transfer allows a low-temperature approach to 3-D integration with high-density interconnectivity. Using the characteristics of this technology, we present the mixed SOI bulk (MSB) design approach that effectively re-maps conventional VLSI designs to the 3-D design space. Tradeoffs in delay, noise margin, power, and circuit footprint are analyzed and demonstrated through analyzes of static, dynamic, pass-transistor, and SRAM circuits.

Are we there yet? Looking beyond the end of scaling in the nanometer era

The major electronic applications of the coming decades and the technology that would make those applications possible are an important subject of discussion for industry and academia. Usefully employing gigantic scale of integration and working around the end of scaling underlie this subject, and in practice, the biggest challenge this faces is in control of power, designability, efficient interconnectivity, and reproducibility in a general purpose technology with provides a useful function. In this talk, I will use speculative examples, establish the practical issues in pursuing the examples, and then discuss from group’s work devices (back-plane and nano-scale), circuits (configurable and power-aware), technologies (three-dimensional), and architectures (configurable) that offer a fruitful direction.