Sandip Tiwari

A silicon nanocrystals based memory

A new memory structure using threshold shifting from charge stored in nanocrystals of silicon (≊5nm in size) is described. The devices utilize direct tunneling and storage of electrons in the nanocrystals. The limited size and capacitance of the nanocrystals limit the numbers of stored electrons. Coulomb blockade effects may be important in these structures but are not necessary for their operation. The threshold shifts of 0.2–0.4 V with read and write times less than 100’s of a nanosecond at operating voltages below 2.5 V have been obtained experimentally. The retention times are measured in days and weeks, and the structures have been operated in an excess of 109 cycles without degradation in performance. This nanomemory exhibits characteristics necessary for high density and low power.

Fast and long retention-time nano-crystal memory

A threshold-shifting, single transistor memory structure with fast read and write times and long retention time is described. The structure consists of a silicon field-effect transistor with nano-crystals of germanium or silicon placed in the gate oxide in close proximity of the inversion surface. Electron charge is stored in these isolated 2-5 nm size nano-crystals which are separated from each other by greater than 5 nm of SiO/sub 2/ and from the inversion layer of the substrate surface by less than 5 nm of SiO/sub 2/. Direct tunneling of charge from the inversion layer and its storage in the nano-crystal causes a shift in the threshold voltage which is detected via current sensing. The nano-crystals are formed using implantation and annealing or using direct deposition of the distributed floating gate region. Threshold shift of 0.3 V is obtained in Ge-implanted devices with 2 nm of SiO/sub 2/ injection layer by a 4 V write pulse of 300 ns duration. The nano-crystal memories achieve improved programming characteristics as a nonvolatile memory as well as simplicity of the single poly-Si-gate process. The V/sub T/ window is scarcely degraded after greater than 10/sup 9/ write/erase cycles or greater than 10/sup 5/ s retention time. Nano-crystal memories are promising for nonvolatile memory applications.

Single charge and confinement effects in nano‐crystal memories

Use of nano‐crystals of silicon in close proximity (1.5–4.5 nm) of a transistor channel lead to structures with pronounced memory where effects due to discrete number of electrons, confinement‐induced subbands in inversion layers and discrete energy states in quantum dots, random charge distribution in quantum dots, and transmission through a strong barrier are very important. Experimental results show plateaus in threshold voltage at low temperatures, spaced nearly equally apart, and indicative of single electron effects. Varying the oxide thickness shows strong influence on speed and charge retention. We confirm the strength of confinement effects and discuss the underlying considerations in the operation of the memory that are related to the reduced volume, strength of the barrier, and random distribution of the trapped charge in nano‐crystals.

Bridging the processor-memory performance gap with 3D IC technology

Microprocessor performance has been improving at roughly 60% per year. Memory access times, however, have improved by less than 10% per year. The resulting gap between logic and memory performance has forced microprocessor designs toward complex and power-hungry architectures that support out-of-order and speculative execution. Moreover, processors have been designed with increasingly large cache hierarchies to hide main memory latency. This article examines how 3D IC technology can improve interactions between the processor and memory. Our work examines the performance of a single-core, single-threaded processor under representative work loads. We have shown that reducing memory latency by bringing main memory on chip gives us near-perfect performance. Three-dimensional IC technology can provide the much needed bandwidth without the cost, design complexity, and power issues associated with a large number of off-chip pins. The principal challenge remains the demonstration of a highly manufacturable 3D IC technology with high yield and low cost.

Volatile and non-volatile memories in silicon with nano-crystal storage

A single transistor memory structure, with changes in threshold voltage exceeding /spl ap/0.25 V corresponding to single electron storage in individual nano-crystals, operating in the sub-3 V range, and exhibiting long term to non-volatile charge storage is reported. As a consequence of Coulombic effects, operation at 77 K shows a saturation in threshold voltage in a range of gate voltages with steps in the threshold voltage corresponding to single and multiple electron storage. The plateauing of threshold shift, operation at ultra-low power, low voltages, and single element implementation utilizing current sensing makes this an alternative memory at speeds lower than those of DRAMs and higher than those of E/sup 2/PROMs, but with potential for significantly higher density, lower power, and faster read.

Room temperature operation of a quantum-dot flash memory

A flash-memory device has been fabricated and demonstrated at room temperature by coupling a self-aligned, sub-50-nm quantum dot to the channel of a transistor on a silicon-on-insulator (SOI) substrate. Large threshold voltage shifts of up to 0.75 V are obtained for small erase/write voltages (13 V) at room temperature. At 90 K, evidence of single electron storage is observed. The small size of this device is attractive for achieving high packing densities, while the relatively large output current (100 nA-/spl mu/As), low off-state current (10 pA), and simple fabrication, requiring only minor variations in standard processing, make it suitable for integration with current silicon memory and logic technology.

Self‐consistent modeling of accumulation layers and tunneling currents through very thin oxides

Poisson and Schrodinger equations are solved self‐consistently for accumulated layers in metal‐oxide‐semiconductor devices and applied to the calculation of tunneling currents at 300 K and 77 K and extraction of parameters for very thin oxides. Calculations at 300 K show strong agreement with measured tunneling currents and also point out the sources of inaccuracies in extracting thicknesses of oxides by electrical methods such as through measurement of capacitance. Direct tunneling current in thin oxides (1.5–2.0 nm) are shown to achieve larger than 1  A /cm2 current density for applied voltages smaller than 3 V, pointing to possibilities of achieving high endurance injection across thin oxides. Comparison of calculations using a classical approach and self‐consistent approach shows fortuitous agreements in tunneling currents despite large differences in the physical models. Appropriate methods for calculating tunneling currents from bound and extended quantum states are also described.

Empirical fit to band discontinuities and barrier heights in III–V alloy systems

We present a figure summarizing the variation of conduction band discontinuity, valence band discontinuity, and gold Schottky barrier height for binary and ternary III–V semiconductors. This figure, which applies to unstrained material, makes use of the property of transitivity in band alignments, and the observed experimental correlation between barrier heights and band gap discontinuities, to consolidate a wide range of data. The figure should be very useful in the design of novel heterostructure electronic and optical devices.

Unpinned GaAs MOS capacitors and transistors

Metal-oxide-semiconductor (MOS) capacitors and field-effect transistors (MOSFETs) in the GaAs semiconductor system using an unpinned interface are described. The structures utilize plasma-enhanced chemical-vapor deposition (PECVD) for the silicon-dioxide insulator on GaAs that has been terminated with a few monolayers of silicon during growth by molecular beam epitaxy. Interface densities in the structures have been reduced to approximately 10/sup 12/ cm/sup -2/.eV/sup -1/. High-frequency characteristics indicate strong inversion of both p-type and n-type GaAs. The excellent insulating quality of the oxide has allowed demonstration of quasi-static characteristics. MOSFETs operating in depletion mode with a transconductance of 60 mS/mm at 8.0- mu m gate lengths have been fabricated.<<ETX>>

Analysis of the operation of GaAlAs/GaAs HBTs

Drift-diffusion modeling in two dimensions has been used to characterize and analyze storage, transport and recombination effects in GaAlAs/GaAs heterostructure bipolar transistors. Both intrinsic and parasitic effects have been studied, and their relationship to the design of the device is discussed. For conventional dopings and high current densities, the heterojunction grading potential causes a barrier in the base-emitter junction, which results in a large increase in the dynamic resistance. In heterojunction collectors, a similar barrier leads to a large increase in base charge storage and to spreading of the collector current. It is shown that increased doping levels can successfully suppress these barrier effects. The capacitance and transport phenomena at the base-emitter junction are also analyzed under conditions of large forward bias, where the junction space-charge region is shorter than the alloy grading length. Recombination is analyzed in the limit of high surface recombination velocities using Shockley-Read-Hall theory in the presence of Fermi-level pinning due to surface states. The pinning results in a potential energy saddle point at the edge of the base-emitter junction, which largely determines the surface recombination behavior of the transistor when the recombination velocity is high. >