Christoph Albrecht

Global routing by new approximation algorithms for multicommodity flow

We show how the new approximation algorithms by Garg and Konemann with extensions due to Fleischer for the multicommodity flow problem can be modified to solve the linear programming relaxation of the global routing problem. Implementation issues to improve the performance, such as a discussion of different functions for the dual variables and how to use the Newton method as an additional optimization step, are given. It is shown that not only the maximum relative congestion is minimized, but the congestion of the edges is distributed equally such that the solution is optimal in a well-defined sense: the vector of the relative congestion of the edges sorted in nonincreasing order is minimal by lexicographic order. This is an important step toward improving signal integrity by extra spacing between wires. Finally, we show how the weighted netlength can be minimized. Our computational results with recent IBM processor chips show that this approach can be used in practice even for large chips and that it is superior on difficult instances where ripup and reroute algorithms fail.

Provably good global routing by a new approximation algorithm for multicommodity flow

We show how that new approximation algorithms by Garg and Konemann for the multicommodity flow problem can be modified to solve the linear programming relaxation of the global routing problem. The algorithm presented here also provides a solution of the dual linear problem, thus gives a lower bound on the optimum maximum relative congestion. Our computation results with recent IBM processor chips show that this approach can be used in practice even for large chips and that it is superior on difficult instances where rip-up and reroute algorithms fail.

Cycle time and slack optimization for VLSI-chips

We consider the problem of finding an optimal clock schedule, i.e. optimal arrival times for clock signals at latches of a VLSI chip. We describe a general model which includes all previously considered models. Then we show how to optimize the cycle time and optimally balance slacks on data paths and on clocktree paths. The problem of finding a clock schedule with the optimum cycle time was solved before, either by linear programming or by binary search, using a test for negative circuits in a digraph as a subroutine. We show for the first time that a direct combinatorial algorithm solves this problem optimally. Incidentally, this yields a new efficient method for timing analysis with transparent latches. Moreover, we extend this algorithm to the slack balancing problem: To make the chip less sensitive to routing detours, process variations and manufacturing skew it is desirable to have as few critical paths as possible. We show how to find the clock schedule with minimum number of critical paths (optimum slack distribution) in a well-defined sense. Rather than fixed dock arrival times we show how to obtain as large as possible intervals for the clock arrival times. This can be considered as slack on clocktree paths. Indeed, we can find the global optimum of simultaneous optimization of slacks on all data paths and clocktree paths. All the above is done by very efficient network optimization algorithms, based on parametric shortest paths. Our computational results with recent IBM processor chips show that the number of critical paths decreases dramatically, in addition to a considerable improvement of the cycle time. The running times are reasonable even for the largest designs.

Maximum mean weight cycle in a digraph and minimizing cycle time of a logic chip

The maximum mean weight cycle problem is well-known: given a digraph G with weights c:E(G) → R, find a directed circuit in G whose mean weight is maximum. Closely related is the minimum balance problem: Find a potential π: V(G) → R such that the numbers slack(e):=π(w)-π(v)-c((v, w))(e=(v, w)∈E(G)) are optimally balanced: for any subset of vertices, the minimum slack on an entering edge should equal the minimum slack on a leaving edge. Both problems can be solved by a parametric shortest path algorithm.We describe an application of these problems to the design of logic chips. In the simplest model, optimizing the clock schedule of a chip to minimize the cycle time is equivalent to a maximum mean weight cycle problem. It is very important to find a solution with well-balanced slacks; this problem, in the simple model, is a minimum balance problem.However, in practical situations many constraints have to be taken into account. Therefore minimizing the cycle time and finding the optimum slack distribution are more general problems. We show how a parametric shortest path algorithm can be extended to solve these problems efficiently.Computational results with recent IBM processor chips show that the cycle time reduces considerably. Moreover, the number of critical paths (with small slack) decreases dramatically. As a result we obtain significantly faster chips. The running time of our algorithm is reasonable even for very large designs.

On the skew-bounded minimum-buffer routing tree problem

Bounding the load capacitance at gate outputs is a standard element in todays electrical correctness methodologies for high-speed digital very large scale integration design. Bounds on load caps improve coupling-noise immunity, reduce degradation of signal transition edges, and reduce delay uncertainty due to coupling noise (Kahng et al. 1998). For clock and test distribution, an additional design requirement is bounding the buffer skew, i.e., the difference between the maximum and the minimum number of buffers over all of the source-to-sink paths in the routing tree, since buffer skew is one of the main factors affecting delay skew (Tellez and Sarrafzadeh 1997). In this paper, we consider algorithms for buffering a given tree with the minimum number of buffers under given load cap and buffer skew constraints. We show that the greedy algorithm proposed by Tellez and Sarrafzadeh is suboptimal for nonzero buffer-skew bounds and give examples showing that no bottom-up greedy algorithm can achieve optimality. The main contribution of the paper is an optimal dynamic programming algorithm for the problem. Experiments on test cases extracted from recent industrial designs show that the dynamic programming algorithm has practical running time and saves up to 37.5% of the buffers inserted by Tellez and Sarrafzadehs algorithm.

Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing

We describe a new algorithm for floorplan evaluation using timing-driven buffered routing according to a prescribed buffer site map. Specifically, we describe a provably good multi-commodity flow based algorithm that finds a global routing minimizing routing area (wirelength and number of buffers) subject to given constraints on buffer/wire congestion and sink delays. This permits detailed floorplan evaluation, i.e. computing the trade-off curve between routing area and wire/buffer congestion under any combination of delay and capacity constraints. Our algorithm (1) enforces maximum source/buffer wireloads; (2) enforces wire and buffer congestion constraints by taking into account routing channel capacities and buffer site locations; (3) enforces individual sink delay constraints; (4) performs buffer/wire sizing and layer assignment; and (5) integrates pin assignment with virtually no increase in runtime. Preliminary experiments show that near-optimal results are obtained with a practical runtime.