Radu Zlatanovici

SRAM Read/Write Margin Enhancements Using FinFETs

Process-induced variations and sub-threshold leakage in bulk-Si technology limit the scaling of SRAM into sub-32 nm nodes. New device architectures are being considered to improve control and reduce short channel effects. Among the likely candidates, FinFETs are the most attractive option because of their good scalability and possibilities for further SRAM performance and yield enhancement through independent gating. The enhancements to read/write margins and yield are investigated in detail for two cell designs employing independently gated FinFETs. It is shown that FinFET-based 6-T SRAM cells designed with pass-gate feedback (PGFB) achieve significant improvements in the cell read stability without area penalty. The write-ability of the cell can be improved through the use of pull-up write gating (PUWG) with a separate write word line (WWL). The benefits of these two approaches are complementary and additive, allowing for simultaneous read and write yield enhancements when the PGFB and PUWG designs are used in combination.

Energy–Delay Optimization of 64-Bit Carry-Lookahead Adders With a 240 ps 90 nm CMOS Design Example

A methodology for energy-delay optimization of digital circuits is presented. This methodology is applied to minimizing the delay of representative carry-lookahead adders under energy constraints. Impact of various design choices, including the carry-lookahead tree structure and logic style, are analyzed in the energy-delay space and verified through optimization. The result of the optimization is demonstrated on a design of the fastest adder found, a 240-ps Ling sparse domino adder in 1 V, 90 nm CMOS. The optimality of the results is assessed against the impact of technology scaling.

A shared-well dual-supply-voltage 64-bit ALU

A shared N-well, dual-supply-voltage 64b ALU module in 0.18/spl mu/m, 1.8V 1P 5M CMOS technology operates at 1.16GHz on a 9mm/sup 2/ die. For a target delay increase of 2.8%, energy savings are 25.3% using dual supplies. An 8.3% increase in delay, saves 33.3% in energy.

First steps towards SAT-based formal analog verification

Boolean satisfiability (SAT) based methods have traditionally been popular for formally verifying properties for digital circuits. We present a novel methodology for formulating a SPICE-type circuit simulation problem as a satisfiability problem. We start with a circuit level netlist, capture the non-linear behavior of the circuits at the transistor level via conservative approximations and transform the simulation problem into a search problem that can be exhaustively explored via a SAT solver. Thus, for DC as well as fixed time-step based transient and periodic steady state (PSS) simulation formulations, the solutions produced by the solver are formal in nature. We also present algorithms for abstraction refinement and smart interval generation to improve the computational efficiency of our proposed solution scheme. We have implemented our ideas into a tool called fSpice which is the first attempt at building a formal SPICE engine. We demonstrate the applicability of our ideas by showing experimental results using pruned versions of real designs that faced challenges during chip tape-out.

A 240ps 64b carry-lookahead adder in 90nm CMOS

A 64b adder with a single-execution cycle time of 250ps is fabricated in a 90nm CMOS technology. The adder is designed using an energy-delay optimization framework that can rapidly optimize different microarchitectures in the energy-delay space. The microarchitecture with the lowest delay, a sparse radix-4 Ling parallel prefix tree, is chosen. The carry tree uses footless domino logic to minimize delay while the non-critical paths use minimum-size static logic to reduce energy. The adder consumes 311mW from a 1V supply

Power – performance optimization for custom digital circuits

This paper presents a modular optimization framework for custom digital circuits in the power – performance space. The method uses a static timer and a nonlinear optimizer to maximize the performance of digital circuits within a limited power budget by tuning various variables such as gate sizes, supply, and threshold voltages. It can employ different models to characterize the components. Analytical models usually lead to convex optimization problems where the optimality of the results is guaranteed. Tabulated models or an arbitrary timing signoff tool can be used if better accuracy is desired and although the optimality of the results cannot be guaranteed, it can be verified against a near-optimality boundary. The optimization examples are presented on 64-bit carry-lookahead adders. By achieving the power optimality of the underlying circuit fabric, this framework can be used by logic designers and system architects to make optimal decisions at the microarchitecture level.

Analog circuit synthesis using standard EDA tools

A design methodology for analog circuit blocks is proposed which combines circuit knowledge and high-level general-purpose math packages with CAD simulation tools. The proposed flow of the design of a complex analog or mixed-signal system starts with a conceptual phase setting performance goals for each block, Followed by an exploration phase based on analytical descriptions resulting in the selection of a performance point in the design space and an implementation phase resulting in the sizing of the transistors in each block. The final phase of the electrical design is verification, optimization and design centering in SPICE using foundry-provided process data. It is shown that numerical optimization available in some SPICE offerings such as Eldo deliver a design that not only meets specifications but delivers optimal performance for a selected objective within given constraints

Power-Performance Optimal DSP Architectures and ASIC Implementation

A hierarchical, sensitivity-based ASIC design methodology is proposed and demonstrated in the implementation of power-performance optimal signal processing kernels for wireless applications. The design approach uses a systematic exploration of the power-performance design tradeoff space at the architecture, micro-architecture, and circuit levels. Energy-efficiency gains achieved via this methodology are exploited to accommodate flexibility to support multi-standard radio architectures. The methodology is exemplified in the selection of architecture and design of a flexible digital finite impulse response (FIR) filter. The flexible FIR filter consumes area and power that is only 2 to 4 times that of a dedicated ASIC FIR.