Christoph Sandner

A 6-bit 1.2-GS/s low-power flash-ADC in 0.13-/spl mu/m digital CMOS

We present a 6-bit 1.2-GS/s flash-ADC with wide analog bandwidth and low power, realized in a standard digital 0.13 /spl mu/m CMOS copper technology. Employing capacitive interpolation gives various advantages when designing for low power: no need for a reference resistor ladder, implicit sample-and-hold operation, no edge effects in the interpolation network (as compared to resistive interpolation), and a very low input capacitance of only 400 fF, which leads to an easily drivable analog converter interface. Operating at 1.2 GS/s the ADC achieves an effective resolution bandwidth (ERBW) of 700 MHz, while consuming 160 mW of power. At 600 MS/s we achieve an ERBW of 600 MHz with only 90 mW power consumption, both from a 1.5 V supply. This corresponds to outstanding figure-of-merit numbers (FoM) of 2.2 and 1.5 pJ/convstep, respectively. The module area is 0.12 mm/sup 2/.

A fully integrated differential CMOS LNA for 3-5-GHz ultrawideband wireless receivers

A fully integrated differential low-power low-noise amplifier (LNA) for ultrawideband (UWB) systems operating in the 3-5-GHz frequency range is presented. A two-section LC ladder input network is exploited to achieve excellent input match in a wideband fashion and to optimize the noise performance. Prototypes fabricated in a digital 0.13-mum complementary metal oxide semiconductor technology show the following performance: 9.5-dB peak power gain, 3.5-dB minimum noise figure, -6-dBm input-referred 1-dB compression point, and -0.8-dBm input-referred third-order intercept point, while drawing 11mA from a 1.5-V supply. The realized LNA is compared with previously reported LNAs tailored for the same frequency range

Transformer-Based Dual-Mode Voltage-Controlled Oscillators

In this brief, we propose to use a transformer-based resonator to build a dual-mode oscillator, e.g., a system capable of oscillating at two different frequencies without recurring to switched inductors, switched capacitors, or varactors. The behavior of the resonator configured as a one-port and a two-port network is studied analytically, and the dependence of the quality factor on the design parameters is thoroughly explored. These results, combined with the use of traditional frequency tuning techniques, are applied to the design of a wide-band voltage-controlled oscillator (VCO) that covers the frequency range 3.6-7.8 GHz. The performance of the designed VCO, implemented in a digital 0.13-mum CMOS technology, has been studied by transistor-level and 2.5D electromagnetic simulation (Agilent Momentum). A typical phase noise performance at 1-MHz offset of -104 dBc/Hz has been predicted, while the power consumption ranges from 1 to 8 mW, depending on the VCO configuration

Analysis and Design of an Integrated Notch Filter for the Rejection of Interference in UWB Systems

A 0.13-mu m CMOS fourth-order notch filter for the rejection of the 5-6 GHz interference in UWB front-ends is reported. The filter is integrated into an analog front-end for Mode #1 UWB. A thorough analysis based on a simplified model of the filter is carried out. An algorithm for the automatic tuning and calibration of the filter is also discussed and demonstrated. Two versions of the circuit are designed and fabricated: the first comprises a low-noise amplifier and the filter, and the second expands it to a complete front-end. In the latter version the filter was also redesigned. The filter provides more than 35 dB of attenuation and has a tuning range of 900 MHz, adding less than 30% power consumption to the LNA. The out-of-band IIP3 (higher than -13.2 dBm with the filter off) takes a 9-dB advantage from the filter and the compression of the gain due to the out-of-band blocker is reduced by at least 6 dB in the complete front-end. The conversion gain of the front-end is 25 dB per channel, its average noise figure is lower than 6.2 dB, and its in-band 1-dB compression point is higher than - 30 dBm at a power consumption of 32 mW.

A WiMedia/MBOA-Compliant CMOS RF Transceiver for UWB

A fully integrated WiMedia/MBOA-compliant RF transceiver for UWB data communication in the 3 to 5GHz band is presented. It is designed in a 0.13mum standard CMOS process with 1.5V single supply voltage. The NF is between 3.6 and 4.1dB over all 3 bands. On the TX side, the P1dB is 5dBm supporting an EVM of -28dB and up to -4dBm output power. A single-PLL LO generation is included

Fully integrated distributed power amplifier in CMOS technology, optimized for UWB transmitters

A power amplifier (PA) using the distributed amplifier technique for the ultra wideband (UWB) standard is presented. The amplifier is fabricated in a standard 0.13 /spl mu/m CMOS technology and comes with on-chip biasing circuitry and a non-distributed input stage. Measurement results are given for a chip-on-board module to take any influence of product assembly into account. It achieves a transmission coefficient S/sub 21/ = 17 dB, a corner frequency of f/sub c/ = 8 GHz and a 1 dB compression point of A/sub 1dB/ = 3.5 dBm. The output impedance is matched to 50 /spl Omega/ so that external matching circuitry can be omitted. With these features, it is customized to be integrated with other building blocks to a fully integrated CMOS UWB transmitter product.

A 3.4-7 GHz Transformer-Based Dual-mode Wideband VCO

In this work, a dual-mode oscillator built around a transformer-based resonator is proposed. By making use of this technique, a wideband VCO is designed that features a 69% tuning range spanning from 3.4 GHz to 7 GHz. An excellent 14.8 dB power-frequency-tuning-normalized figure of merit, accounting of -118.6 dBc/Hz phase noise at 1 MHz offset from the 4.6 GHz carrier at 1 mW power consumption, is reported

A subpicosecond jitter PLL for clock generation in 0.12-/spl mu/m digital CMOS

A fully integrated subpicosecond jitter phase-locked loop (PLL)-based frequency synthesizer in a standard digital 0.12-/spl mu/m CMOS technology with 1.5-V supply is presented. Two differentially tuned LC-VCOs are implemented to support different standards for serial data transmission. A fully differential charge pump and an active loop filter are used for reduction of charge-pump current mismatch. Operating with a 311-MHz reference clock, the PLL achieves typically 860-fs integrated jitter, and a phase noise of -115 dBc/Hz at 1-MHz offset, on a 2.488-GHz output. The power consumption is 35 mW, and the area is 0.7 mm/sup 2/.

UWB Fast-Hopping Frequency Generation Based on Sub-Harmonic Injection Locking

Sub-harmonic injection locking is employed to generate the fast-hopping carriers required in UWB systems for WiMedia . A very small area 90-nm CMOS prototype synthesizes the frequencies of band group #6 with a hop time shorter than 4 ns . It occupies 0.074 mm2 and draws 30 mA from a 1.2 V supply. Phase noise at 8.71 GHz is -112 dBc/Hz at 1 MHz offset. The design is supported by a thorough analysis that emphasizes the tradeoffs in the parameters of the proposed system.

A 0.13/spl mu/m CMOS LNA with Integrated Balun and Notch Filter for 3-to-5GHz UWB Receivers

A 0.13mum CM0S LNA for 3-to-5GHz UWB receivers embedding an integrated balun is reported. The LNA includes an integrated notch filter to mitigate the interference of WLAN blockers both in the UNII and ISM bands. Measured performance includes: voltage gain of 19.4dB, S11 < -10dB over the entire band, P1dB > -9.4dBm, and maximum notch filter attenuation of 44dB. The LNA and the notch filter consume 24mW and 7.5mW, respectively.