Christophe Erdmann

6.3 A Heterogeneous 3D-IC consisting of two 28nm FPGA die and 32 reconfigurable high-performance data converters

A reconfigurable heterogeneous 3D-IC is assembled from two 28 nm FPGA die with 580 k logic cells and two 65 nm mixed signal die on a 65 nm interposer in a 35 mm 2 CS-BGA package. One mixed signal die consists of sixteen 16 bit current steering DACs, the other die consists of sixteen 13 bit pipelined ADCs. The interposer provides optimal system partitioning; noise isolation and high density interconnect between subsystems. Receive SNDR > 61.6 dBFS to Nyquist at 500 MS/s and transmit SFDR > 63.8 dBc to 400 MHz at 1.6 GS/s is measured. Ultralow FPGA to converter die interface power of 0.3 mW/Gb/s is achieved and measured digital to analog isolation > 92dB. The solution can be dynamically optimized for channel count, power and speed.

16.1 A 13b 4GS/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC

In recent years, the need for high performance RF sampling ADCs has driven impressive developments of pipelined-SAR and pipelined ADCs, all supported by time-interleaving [1–4]. All these designs use a closed loop MDAC amplifier in the first stage and digital calibration/equalization to alleviate finite gain, settling and memory effects, but the closed-loop amplifier remains a scaling bottleneck. In this work, a three-stage asynchronous pipelined-SAR with open-loop integrator-based amplifiers is used to maximize the sampling frequency, resolution and linearity. The solution is mostly supported by dynamic circuits and multiple calibration loops to reduce cost, power and noise, maximize process portability and support production testability.

16.3 A 330mW 14b 6.8GS/s dual-mode RF DAC in 16nm FinFET achieving −70.8dBc ACPR in a 20MHz channel at 5.2GHz

Direct-RF synthesis has gained increasing attention in recent years [1] [2] as it simplifies the transmitter system by eliminating the intermediate frequency stage. It also offers the opportunity to address the extensive range of cellular bands with the same architecture and building blocks. Direct synthesis of carriers in the 5 to 6GHz unlicenced bands remains a challenge for RF-DACs operating in the 1st Nyquist band, as sampling rates in excess of 12GS/s are required. A more power efficient way to synthesize directly these frequencies is to use wideband mixing-DACs, which increase the output power in the 2nd and 3rd Nyquist bands [3]. In [3] the mixing is done using the quad-switch configuration, which doubles the number of switches and drivers, directly impacting the overall DAC width. In [4] the mixer is inserted in-line between the current cell switch and the output cascode, which requires additional headroom in the output stage. Both implementations impact the overall performance and power of the DAC even when the mixing operation is not used.