Bob Verbruggen

A 40 nm CMOS 0.4–6 GHz Receiver Resilient to Out-of-Band Blockers

A highly-linear software-defined radio operating from 400 MHz to 6 GHz is presented, with the purpose of removing any dedicated filtering at the antenna. Very high resilience to out-of-band interference is achieved thanks to a 2.5 V linear LNA and mixer-based RF blocker filter. The 2 mm2, 40 nm digital CMOS receiver achieves +10 dBm out-of-band IIP3 and >; +70 dBm calibrated IIP2 at 3 dB NF. It tolerates 0 dBm blockers at 20 MHz offset with acceptable blocker NF.

A 2.2 mW 1.75 GS/s 5 Bit Folding Flash ADC in 90 nm Digital CMOS

A 5 bit 1.75 GS/s ADC using a factor 2 dynamic folding technique is presented. The 2X folding lowers the number of comparators from 31 to 16, simplifies encoding and reduces power consumption and area. The comparators in this converter are implemented with built-in references and calibration to further reduce power consumption. INL and DNL after calibration are smaller than 0.3 LSB, with an SNDR of 29.9 dB at low frequencies, and above 27.5 dB up to the Nyquist frequency. The converter consumes 2.2 mW from a 1 V supply, yielding a FoM of 50 fJ per conversion step and occupies 0.02 mm2 in a 90 nm 1P9M digital CMOS process.

A 2.4 GHz Low-Power Sixth-Order RF Bandpass

A sixth-order RF bandpass DeltaSigma ADC operating on the 2.4 GHz ISM band, which is suitable for RF digitization is presented. The bandpass loop filter is based on digitally programmable Gm-LC resonators that can be calibrated online to adjust the RF center frequency. By sampling below the input Nyquist frequency, the clock in the system was reduced to 3 GHz, allowing a large reduction of the power consumption. Implemented in a standard 90 nm CMOS process, the IC achieves 40 dB and 62 dB of SNDR and SFDR, respectively, on a 60 MHz bandwidth with 40 mW of power consumption leading to a FoM of 245 GHz/W (4.1 pJ/conversion step). This implementation paves a possible way towards direct RF digitization receiver architectures.

\Delta\Sigma

In recent years the energy efficiency of A/D converters has been improved significantly. Only 5 years ago [3] an energy efficiency of 1 pJ/conversion step was considered state-of-the-art. Now power efficiencies are reported in f J/conversion step. In this paper two new converter techniques are presented that further improve upon reported energy efficiencies of A/D converters. The first technique implements the quantization with a comparator-based asynchronous binary search (CABS). The second technique implements the SAR control algorithm on the comparators (SAR-CC) that are also used to do the quantization. Both these techniques have been applied in a fully dynamic 7 bit A/D converter that uses a two-step lb coarse and 6b fine architecture [2]. The 1b coarse converter is implemented using the SAR-CC principle, the 6b fine converter is implemented using the CABS principle. The 7 bit prototype implementation in 90 nm digital CMOS on a 1 V supply achieves 6.4ENOB, 40 dB SNDR at 150 MS/s consuming 133 muW giving 10 fJ/conversion step energy efficiency (FOM). A second prototype implementing a stand-alone 6b CABS converter (the sub-A/D converter of the 7 bit converter) achieves 32 dB SNDR at 250 MS/s with 140 muW of power consumption, which results in a FOM of 15 fJ/conversion step.

Converter in CMOS

High-speed low-resolution ADCs are an essential part of receivers for wireless standards such as UWB. These converters have to combine the stringent speed specifications with the demand for low power consumption. Flash architectures are often chosen because they offer the largest speed. However, in this architecture, area and power depend exponentially on the resolution since the comparators are often the largest contributor to the overall power consumption. Folding is a well-known technique used to reduce the number of comparators in an ADC while maintaining high speed. It was previously implemented by generating a number of zero crossings with folding amplifiers, often in combination with interpolation or averaging. In this design, a folding factor of 2 is realized as in but with only dynamic power consumption and without using amplifiers. This reduces the number of comparators from 31 to 16 for a 5b resolution.

A 150 MS/s 133

SDRs come of age ([1,2]) and transcend beyond just acquiring the reconfigura-bility to replace any standard radio: they develop toward systems where a simplified antenna interface can be used, with most dedicated filtering removed. This requires a receiver accommodating much higher linearity and resilience against out-of-band interference than a standard radio, still achieving competitive sensitivity (especially in the absence of interference). Mixer-first front-ends with excellent linearity have been reported [3]. However, their NF (including 1/f in absence of the LNA gain) is not competitive, and they may suffer from large LO feedthrough to the antenna (LOFT). Moreover they lack receiver functionality such as gain and filtering, which cannot be simply added without compromising linearity. A receiver with mixer-at-the-antenna-based bandpass filter [4] similarly may suffer from LOFT and increased N F. This work presents a full software-defined receiver with 3dB NF that tolerates 0dBm blockers with acceptable blocker NF at maximum gain. It achieves +10dBm out-of-band (OB) IIP3 and >+70dBm IIP2. Such a receiver is to operate using no other than harmonic-rejection filtering.

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A 2.2 GS/s 4×-interleaved 6b ADC in 40 nm digital CMOS is presented. Each ADC slice consists of a 1b folding stage followed by a pipelined binary-search sub-ADC using dynamic nonlinear amplifiers for low power consumption and high speed. The folding stage samples the input, removes its common-mode component and rectifies the differential voltage. The pipelined binary-search sub-ADC leverages threshold calibration to correct for amplifier and comparator imperfections, which allows the use of inherently nonlinear dynamic amplifiers. The prototype achieves 31.6 dB SNDR at 2.2 GS/s with a 2 GHz ERBW for 2.6 mW power consumption in an area of 0.03 mm2.

W 7 bit ADC in 90 nm Digital CMOS

In this paper, a 2-step 7b ADC consists of a TVH, followed by a 1b comparison and D/A conversion, and a 6b comparator-based asynchronous binary-search (CABS) conversion. The 7b ADC operates as follows: the passive T/H samples the input signal on a capacitance, the 1b comparator determines the sign of the input and steers a capacitive DAC. The DAC subtracts 1/4 of the full-scale range in charge from one of the input nodes, changing simultaneously differential signal and common-mode level to be in range of the 6b CABS converter. The clock buffer generates the 1b coarse A/D clock signal and starts the 6b fine conversion after the 1b D/A conversion has finished.

A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nm Digital CMOS

Communication in the unlicensed frequency band around 60GHz requires a very fast ADC with low resolution. We present a four-way interleaved converter, of which one channel is shown in Fig. 16.3.1, for these requirements. Dynamic pipelined conversion enables low power quantization at high speed with low input capacitance but requires calibration. A folding front-end halves the required calibration effort.

A 40nm CMOS highly linear 0.4-to-6GHz receiver resilient to 0dBm out-of-band blockers

CMOS downscaling in the nanoscale era will necessitate drastic changes to the planar bulk CMOS transistor to keep pace with the required speed increase while at the same time maintaining acceptable performance in terms of leakage, variability and analog parameters such as gain, noise and linearity. For the gate electrode and the gate dielectric, which classically use polysilicon and with some amount of nitridation, new materials might be needed. Also, a new transistor architecture might be required that deviates from the planar structure. Thanks to their inherent suppression of short-channel effects, reduced drain-induced barrier lowering and good scalability, multi-gate devices such as fin-shaped field-effect transistors (FinFETs) are considered as possible candidates for device scaling at the end of International Technology Roadmap for Semiconductors. As such, they form a first step between a planar architecture and a silicon nanowire. In this paper, we demonstrate with functional prototypes of analog and RF circuits that the combination of a new gate stack with a FinFET transistor architecture outperforms comparable circuit realizations in planar bulk CMOS for low to moderate speed. Further, the FinFETs exhibit less leakage and show less intra-die variability than their planar bulk counterpart. In the microwave and millimeter-wave frequency region, planar bulk CMOS is still superior. The main challenge for FinFET performance in the coming years is the improvement of the maximum cutoff frequency, which is nowadays limited to 100 GHz.