Christophe Jego

Design and FPGA prototyping of a bit-interleaved coded modulation receiver for the DVB-T2 standard

Signal Space Diversity (SSD) has been lately adopted into the second generation of the terrestrial digital video broadcasting standard DVB-T2. In this paper, a bit-interleaved coded modulation receiver for the DVB-T2 standard is detailed. An LDPC decoder based on a vertical layered schedule is the main novelty of this work. It enables an efficient exchange of extrinsic information between the rotated demapper and the LDPC decoder if an iterative receiver is considered. The design and the FPGA prototyping of the resultant architecture are then described. Low architecture complexity and good performance represent the main features of the proposed receiver.

Reed-Solomon turbo product codes for optical communications: from code optimization to decoder design

Turbo product codes (TPCs) are an attractive solution to improve link budgets and reduce systems costs by relaxing the requirements on expensive optical devices in high capacity optical transport systems. In this paper, we investigate the use of Reed-Solomon (RS) turbo product codes for 40 Gbps transmission over optical transport networks and 10 Gbps transmission over passive optical networks. An algorithmic study is first performed in order to design RS TPCs that are compatible with the performance requirements imposed by the two applications. Then, a novel ultrahigh-speed parallel architecture for turbo decoding of product codes is described. A comparison with binary Bose-Chaudhuri-Hocquenghem (BCH) TPCs is performed. The results show that high-rate RS TPCs offer a better complexity/performance tradeoff than BCH TPCs for low-cost Gbps fiber optic communications.

A highly parallel Turbo Product Code decoder without interleaving resource

This article presents an innovative turbo product code (TPC) decoder architecture without any interleaving resource. This architecture includes a full-parallel SISO decoder able to process n symbols in one clock period. Syntheses show the better efficiency of such an architecture compared with existing previous solutions. Considering a 6-iteration turbo decoder of a (32,26)2 BCH product code, synthetized in a 90 nm CMOS technology, the resulting information throughput is 2.5 Gb/s with an area of 233 Kgates. Finally a second architecture enhancing parallelism rate is described. The information throughput is 33.7 Gb/s while an area estimation gives A=10 mum2.

Blind Frame Synchronization of Product Codes Based on the Adaptation of the Parity Check Matrix

We present in this paper a blind frame synchronization method based on the adaptation of the parity check matrix of the code. The blind synchronizer is initially based on the calculation of the Log-Likelihood Ratios (LLR) of the syndrome elements, obtained using the parity check matrix of the code. Before applying our synchronization procedure, we propose in this paper to rearrange the parity check matrix of the code according to the reliability of the received symbols as previously introduced for decoding linear block codes with high density parity check matrix. Simulation results show that the Frame Error Rate (FER) curves obtained after applying the proposed synchronization method to product codes are very close to the ones with perfect synchronization. In addition to its powerful synchronization properties, the main advantage of the proposed synchronization algorithm is its capability of being introduced as a part of the decoder so that no additional material is required for the synchronization step.

Architecture dedicated to the MMSE equalizer of iterative receiver for linearly precoded MIMO systems

This paper presents an architectural solution for a MMSE equalizer of iterative receiver for linearly precoded MIMO systems. Two transmit antennas, two receive antennas, and a preceding size of two were chosen for the linearly precoded MIMO system. Thanks to the orthogonality property of Hadamard matrix that is used for the linear preceding and the block-fading nature of the MIMO channel, the inversion of the 4times4 covariance matrix can be done by inverting a single 2times2 matrix only once per data block. A survey of matrix inversion, which is the critical part of the MMSE equalizer is presented and different architectures are compared. We show that the direct analytical method gives the more efficient architectures to invert small matrices, typically 2times2 or 4times4. Furthermore, an architectural design and a time analysis for the MMSE equalizer are detailed. Each block of the architecture was designed to achieve a throughput of two complex estimated symbols per time cycle at the output of the MMSE equalizer.

Design and implementation of a soft-decision decoder for Cortex codes

Cortex codes are a family of rate-1/2 self-dual systematic linear block codes with good distance properties. This paper investigates the challenging issue of designing an efficient soft-decision decoder for Cortex codes. A dedicated algorithm is introduced that takes advantage of the particular structure of the code to simplify the decoding. Simulation results show that the proposed algorithm achieves an excellent trade-off between performance and complexity for short Cortex codes. A decoder architecture for the (32,16,8) Cortex code based on the (4,2,2) Hadamard code has been successfully designed and implemented on FPGA device. To our knowledge, this is the first efficient digital implementation of a soft-decision Cortex decoder.

On the higher efficiency of parallel Reed-Solomon turbo-decoding

In this paper, we demonstrate the higher hardware efficiency of Reed-Solomon (RS) parallel turbo decoding compared with BCH parallel turbo decoding. Based on an innovative architecture, this is the first implementation of fully parallel RS turbo decoder. A performance analysis is performed showing that RS block turbo codes (RS-BTC) have decoding performance equivalent to Bose Ray-Chaudhuri Hocquenghem-block turbo codes (BCH-BTC). A ratio between the decoder throughput and the decoder area is used to show the higher efficiency of the RS full parallel turbo decoder. Finally an implementation of a (31,29)2 RS block turbo decoder on a high performance board including 6 Xilinx Virtex5 FPGAs is detailed. The resulting turbo decoder has an information throughput above 6 Gb/s while the working frequency is only 45 MHz. It shows that RS BTC are an attractive solution for low cost Gb/s fiber optical communications.