Christophe Lallement

Charge-Based Modeling of Junctionless Double-Gate Field-Effect Transistors

We derived an analytical model for the junctionless double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) device, the principle of which has been recently demonstrated. Despite some similarities with classical junction-based DG MOSFETs, the charge-potential relationships are quite different and cannot be merely mapped on existing multigate formalisms. This is particularly true for the technological parameters of interest where reported doping densities exceed 1019 cm-3 for 10- and 20-nm silicon channel thicknesses. Assessment of the model with numerical simulations confirms its validity for all regions of operation, i.e., from deep depletion to accumulation and from linear to saturation.

VHDL-AMS and Verilog-AMS as alternative hardware description languages for efficient modeling of multidiscipline systems

This paper focuses on commonalities and differences between the two mixed-signal hardware description languages, VHDL-AMS and Verilog-AMS, in the case of modeling heterogeneous or multidiscipline systems. The paper has two objectives. The first one is modeling the structure and the behavior of an airbag system using both the VHDL-AMS and the Verilog-AMS languages. Such a system encompasses several time abstractions (i.e., discrete-time and continuous-time), several disciplines, or energy domains (i.e., electrical, thermal, optical, mechanical, and chemical), and several continuous-time description formalisms (i.e., conservative-law and signal-flow descriptions). The second objective is to discuss the results of the proposed modeling process in terms of the descriptive capabilities of the VHDL-AMS and Verilog-AMS languages and of the generated simulation results. The tools used are the Advance-MS from Mentor Graphics for VHDL-AMS and the AMS Simulator from Cadence Design Systems for Verilog-AMS. This paper shows that both languages offer effective means to describe and simulate multidiscipline systems, though using different descriptive approaches. It also highlights current tool limitations, since full language definitions are not yet supported.

CNTFET Modeling and Reconfigurable Logic-Circuit Design

This paper examines aspects of design technology required to explore advanced logic-circuit design using carbon nanotube field-effect transistor (CNTFET) devices. An overview of current types of CNTFETs is given and highlights the salient characteristics of each. Compact modeling issues are addressed and new models are proposed implementing: 1) a physics-based calculation of energy conduction sub-band minima to allow a realistic analysis of the impact of CNT helicity and radius on the dc characteristics; 2) descriptions of ambipolar behavior in Schottky-barrier CNTFETs and ambivalence in double-gate CNTFETs (DG-CNTFETs). Using the available models, the influence of the parameters on the device characteristics were simulated and analyzed. The exploitation of properties specific to CNTFETs to build functions inaccessible to MOSFETs is also described, particularly with respect to the use of DG-CNTFETs in fine-grain reconfigurable logic.

A simple efficient model of parasitic capacitances of deep-submicron LDD MOSFETs

Abstract Estimation of parasitic capacitances in a MOSFET device is very important, notably in mixed circuit simulation. For deep-submicron LDD MOSFETs, the extrinsic capacitance (overlap plus fringing capacitances) is a growing fraction of the total gate capacitance. A correct estimation of the extrinsic capacitance requires an accurate modeling of each of its constituents. However the major existing models do not correctly predict the overlap capacitance and the inner fringing capacitance (which is often ignored). In this paper a new approach to model the overlap Cov and fringing Cif+Cof capacitances in the zero-current regime is presented. The bias dependence of the extrinsic capacitance is investigated and a detailed study of the influence of the LDD doping dose is also undertaken. Then, an efficient, simple and continuous model describing the evolution of overlap and fringing capacitances in all operating regimes of a n-channel LDD MOSFET is developed. Finally this model is incorporated in an existing compact-model for circuit simulation. It is shown that this new model leads to excellent results in comparison with full 2D numerical device simulation.

Generalization of the Concept of Equivalent Thickness and Capacitance to Multigate MOSFETs Modeling

In this letter, we propose to introduce the notion of equivalent capacitance and to generalize the so-called equivalent-thickness concept to model arbitrary shapes of lightly doped nonplanar multigate MOSFETs, without the need to introduce any unphysical parameter. These definitions, which merely map a multigate geometry into the symmetric double-gate (DG) MOSFET topology, have been validated by extensive comparison with 3-D numerical simulations of quadruple-gate, triple-gate (TG), triangular gate, cylindrical gate-all-around, and DG Fin Field Effect Transistors (FinFETs). Based on this modeling approach, any multigate architecture inherits of the fundamental relationships that have been developed for planar DG MOSFETs, including the normalization of all electrical quantities that considerably simplifies its analysis. In addition, considering a constant mobility, we find that the model can predict electrical characteristics of FinFETs from 275 to 425 K, without the need for any additional parameters. Finally, we were able to predict electrical measurements of a TG MOSFET, making of this generic model an interesting candidate for a design-oriented compact model for arbitrary multigate MOSFETs geometries.

Accounting for quantum effects and polysilicon depletion from weak to strong inversion in a charge-based design-oriented MOSFET model

This paper presents a simple, physics-based, and continuous model for the quantum effects and polydepletion in deep-submicrometer MOSFETs with very thin gate oxide thicknesses. This analytical design-oriented MOSFET model correctly predicts inversion and depletion charges, transcapacitances, and drain current, from weak to strong inversion and from nonsaturation to saturation. One single additional parameter is used for polysilicon doping concentration, while the quantum correction does not introduce any new parameter. Comparison to experimental data of deep-submicrometer technologies is provided, showing accurate fits both for I-V and C-V data. The model offers simple relationships among effective electrical parameters and physical device parameters, providing insight into the physical phenomena. This new model thereby supports device engineering, analog circuit design practice, as well as efficient circuit simulation.

Design-oriented compact models for CNTFETs

This paper deals with the compact modeling of an emerging technology: the carbon nanotube field-effect transistor (CNTFET). The paper proposed two design-oriented compact models, the first one for CNTFET with a classical behavior (MOSFET-like CNTFET), and the second one for CNTFET with an ambipolar behavior (Schottky-barrier CNTFET). Both models have been compared with exact numerical simulations and then implemented in VHDL-AMS

A Common Core Model for Junctionless Nanowires and Symmetric Double-Gate FETs

In this paper, we evidence the link between the planar and cylindrical junctionless field effect transistors (JL-FETs) from the electrostatics and current point of view. In particular, we show that an approximate solution of the Poisson-Boltzmann equation for JL nanowires can be mapped on the planar double-gate topology generating only negligible mismatch, meaning that both devices can share the same core model as far as long channels are considered. These preliminary results are a first step toward a unification of compact models for JL-FETs.

Explicit Compact Model for Ultranarrow Body FinFETs

An explicit charge-based compact model for lightly doped FinFETs is proposed. This design-oriented model is valid and continuous in all operating regimes (subthreshold, linear, and saturation) for channel lengths (L) down to 25 nm, Fin widths (W Si) down to 3 nm, and Fin heights (H Si) down to 50 nm with a single set of parameters. It takes short-channel effects, subthreshold slope degradation, drain-induced barrier lowering, drain saturation voltage with velocity saturation, channel length modulation, and quantum mechanical effects into account.

Synthetic biology methodology and model refinement based on microelectronic modeling tools and languages.

In microelectronics, the design of new systems is based on a proven time-tested design flow. The goal of this paper is to determine to what extend this design flow can be adapted to biosystem design. The presented methodology is based on a top-down approach and consists of starting with a behavioral description of the system to progressively refine it to its final low-level system representation, composed of DNA parts. To preserve accuracy and simplicity, the design flow relies on refined models of biological mechanisms, which can be expressed by the hardware description languages and simulation tools traditionally used in microelectronics. A case study, the complete modeling of a priority encoder, is presented to demonstrate the effectiveness of the method.