Fabien Prégaldiny

Charge-Based Modeling of Junctionless Double-Gate Field-Effect Transistors

We derived an analytical model for the junctionless double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) device, the principle of which has been recently demonstrated. Despite some similarities with classical junction-based DG MOSFETs, the charge-potential relationships are quite different and cannot be merely mapped on existing multigate formalisms. This is particularly true for the technological parameters of interest where reported doping densities exceed 1019 cm-3 for 10- and 20-nm silicon channel thicknesses. Assessment of the model with numerical simulations confirms its validity for all regions of operation, i.e., from deep depletion to accumulation and from linear to saturation.

CNTFET Modeling and Reconfigurable Logic-Circuit Design

This paper examines aspects of design technology required to explore advanced logic-circuit design using carbon nanotube field-effect transistor (CNTFET) devices. An overview of current types of CNTFETs is given and highlights the salient characteristics of each. Compact modeling issues are addressed and new models are proposed implementing: 1) a physics-based calculation of energy conduction sub-band minima to allow a realistic analysis of the impact of CNT helicity and radius on the dc characteristics; 2) descriptions of ambipolar behavior in Schottky-barrier CNTFETs and ambivalence in double-gate CNTFETs (DG-CNTFETs). Using the available models, the influence of the parameters on the device characteristics were simulated and analyzed. The exploitation of properties specific to CNTFETs to build functions inaccessible to MOSFETs is also described, particularly with respect to the use of DG-CNTFETs in fine-grain reconfigurable logic.

A simple efficient model of parasitic capacitances of deep-submicron LDD MOSFETs

Abstract Estimation of parasitic capacitances in a MOSFET device is very important, notably in mixed circuit simulation. For deep-submicron LDD MOSFETs, the extrinsic capacitance (overlap plus fringing capacitances) is a growing fraction of the total gate capacitance. A correct estimation of the extrinsic capacitance requires an accurate modeling of each of its constituents. However the major existing models do not correctly predict the overlap capacitance and the inner fringing capacitance (which is often ignored). In this paper a new approach to model the overlap Cov and fringing Cif+Cof capacitances in the zero-current regime is presented. The bias dependence of the extrinsic capacitance is investigated and a detailed study of the influence of the LDD doping dose is also undertaken. Then, an efficient, simple and continuous model describing the evolution of overlap and fringing capacitances in all operating regimes of a n-channel LDD MOSFET is developed. Finally this model is incorporated in an existing compact-model for circuit simulation. It is shown that this new model leads to excellent results in comparison with full 2D numerical device simulation.

Generalization of the Concept of Equivalent Thickness and Capacitance to Multigate MOSFETs Modeling

In this letter, we propose to introduce the notion of equivalent capacitance and to generalize the so-called equivalent-thickness concept to model arbitrary shapes of lightly doped nonplanar multigate MOSFETs, without the need to introduce any unphysical parameter. These definitions, which merely map a multigate geometry into the symmetric double-gate (DG) MOSFET topology, have been validated by extensive comparison with 3-D numerical simulations of quadruple-gate, triple-gate (TG), triangular gate, cylindrical gate-all-around, and DG Fin Field Effect Transistors (FinFETs). Based on this modeling approach, any multigate architecture inherits of the fundamental relationships that have been developed for planar DG MOSFETs, including the normalization of all electrical quantities that considerably simplifies its analysis. In addition, considering a constant mobility, we find that the model can predict electrical characteristics of FinFETs from 275 to 425 K, without the need for any additional parameters. Finally, we were able to predict electrical measurements of a TG MOSFET, making of this generic model an interesting candidate for a design-oriented compact model for arbitrary multigate MOSFETs geometries.

Design-oriented compact models for CNTFETs

This paper deals with the compact modeling of an emerging technology: the carbon nanotube field-effect transistor (CNTFET). The paper proposed two design-oriented compact models, the first one for CNTFET with a classical behavior (MOSFET-like CNTFET), and the second one for CNTFET with an ambipolar behavior (Schottky-barrier CNTFET). Both models have been compared with exact numerical simulations and then implemented in VHDL-AMS

Explicit Compact Model for Ultranarrow Body FinFETs

An explicit charge-based compact model for lightly doped FinFETs is proposed. This design-oriented model is valid and continuous in all operating regimes (subthreshold, linear, and saturation) for channel lengths (L) down to 25 nm, Fin widths (W Si) down to 3 nm, and Fin heights (H Si) down to 50 nm with a single set of parameters. It takes short-channel effects, subthreshold slope degradation, drain-induced barrier lowering, drain saturation voltage with velocity saturation, channel length modulation, and quantum mechanical effects into account.

Compact modeling of magnetic tunnel junction

A new compact model of a magnetic tunnel junction (MTJ) is presented in this paper. This model is intended to describe the behavior of a MTJ and to take the magnetic as well as the non-linear electronic transport phenomena into account. It should be suitable for circuits simulation and thus, it must be simple (no finite element approach, analytical current versus voltage characteristic only). For this purpose, some assumptions are made. The MTJ model is separated in two entities. The first one concerns the magnetization of a ferromagnetic thin film. The other focuses on the electrical conduction of a MTJ. Both models are implemented and coupled in VHDL-AMS in order to obtain the compact model of a MTJ, which is parameterized with 25 values (19 physical parameters and 6 semi-empirical ones). The first simulations are encouraging. They allow to retrieve classical results on MTJ and to predict interesting behaviors.

The Equivalent-Thickness Concept for Doped Symmetric DG MOSFETs

In this paper, we propose to derive an analytical model for the doped symmetric double-gate (DG) MOSFET that is valid in all regions of operation. We show that doping the silicon channel can be converted in an equivalent silicon thickness and threshold voltage shift using a formalism developed for the undoped device. Adopting the same physical parameters, we demonstrate that this approach is in agreement with numerical technology computer-aided design simulations. This concept is therefore an interesting basis for a unified model for doped and undoped symmetric DG MOSFETs.

Compact Modeling and Applications of CNTFETs for Analog and Digital Circuit Design

This paper presents some case-studies of an emerging nano-device, the carbon nanotube field-effect transistor (CNT-FET). First, we propose two design-oriented compact models, for both unipolar and ambipolar CNTFETs, i.e. devices with a classical behavior (MOSFET-like CNTFET) and an ambipolar behavior (Schottky-Barrier CNTFET). Models have been compared with exact numerical simulations and implemented in VHDL-AMS. Then we show some possible applications of CNTFETs in both digital and analog circuit design. In particular, an analog circuit based on the very particular ID-VGS characteristic of the ambipolar CNTFET is demonstrated.

Quantum compact model for ultra-narrow body FinFET

Quantum mechanical effects (QME) are very significant in undoped (or lightly doped) FinFET with ultra-narrow silicon body. In this work, we present an explicit modeling of QME well-suited for FinFET compact modeling. Our model accounts for the Fin width dependence and predicts with accuracy the increase of threshold voltage and the decrease of drain saturation current due to QME. The modeling of both transconductance and output conductance gives evidence for the continuity and the differentiability of the model. Comparison with 3-D numerical simulations performed for different Fin widths shows the good behavior of the model in all regimes of FinFET operation.