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Dive into the research topics where Christopher A. Poirier is active.

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Featured researches published by Christopher A. Poirier.


IEEE Journal of Solid-state Circuits | 2006

Power and temperature control on a 90-nm Itanium family processor

Rich Mcgowen; Christopher A. Poirier; Chris Bostak; Jim Ignowski; Mark Millican; Warren H. Parks; Samuel Naffziger

This paper describes the embedded feedback and control system on a 90-nm Itanium family processor, code-named Montecito, that maximizes performance while staying within a target power and temperature (PT) envelope. This system, referred to as Foxton Technology (FT), utilizes on-chip sensors and an embedded microcontroller to measure PT and modulate both voltage and frequency (VF) to optimize performance while meeting PT constraints. Changing both VF takes advantage of the cubic relationship of P/spl prop/CV/sup 2/F. We present measured results that show a 31% reduction in power for only a 10% drop in frequency. Montecito is able to implement FT using only 0.5% of the die area and 0.5% of the die power.


international solid-state circuits conference | 2011

A 32 nm, 3.1 Billion Transistor, 12 Wide Issue Itanium® Processor for Mission-Critical Servers

Reid James Riedlinger; Ron Arnold; Larry Biro; Bill Bowhill; Jason Crop; Kevin Duda; Eric S. Fetzer; Olivier Franza; Tom Grutkowski; Casey Little; Charles Morganti; Gary Moyer; Ashley Munch; Mahalingam Nagarajan; Cheolmin Parks; Christopher A. Poirier; Bill Repasky; Edi Roytman; Tejpal Singh; Matthew W. Stefaniw

The next generation in the Intel<sup>®</sup> Itanium<sup>®</sup> processor family, code named Poulson, has eight multi-threaded 64 bit cores. Poulson is socket compatible with the current Intel® Itanium<sup>®</sup> Processor 9300 series (Tukwila). The new design integrates a ring-based system interface derived from portions of previous Xeon<sup>®</sup> and Itanium<sup>®</sup> processors, and includes 32MB of Last Level Cache (LLC). The processor is designed in Intel<sup>®</sup>s 32nm CMOS technology utilizing high-K dielectric metal gate transistors combined with nine layers of copper interconnect. The 18.2x29.9mm<sup>2</sup> die contains 3.1 billion transistors, with 720 million allocated to the eight cores. A total of 54MB of on die cache is distributed throughout the core and system interface. Poulson implements twice as many cores as Tukwila while lowering the thermal design power (TDP) by 15Wto 170W and increases the top frequency of the I/O and memory inter faces by 50% to 6.4GT/s.


international solid-state circuits conference | 2005

Power and temperature control on a 90nm Itanium/sup /spl reg//-family processor

Christopher A. Poirier; R. McGowen; Chris Bostak; Samuel Naffziger

This paper describes the embedded feedback and control system on a 90 nm Itanium/spl reg/-family processor, code-named Montecito, that maximizes performance while staying within a target power and temperature (PT) envelope. This system utilizes on-chip sensors and an embedded micro-controller to measure PT and modulate voltage and frequency to meet PT constraints.


Archive | 2003

System and method to adjust voltage

Samuel D. Naffziger; Shahram Ghahremani; Christopher A. Poirier


Archive | 2003

System for and method of controlling a VLSI environment

Christopher A. Poirier; Samuel D. Naffziger; Christopher J. Fort Collins Bostak


Archive | 2003

Method for measuring integrated circuit processor power demand and associated system

Christopher A. Poirier; Samuel D. Naffziger; Christopher J. Fort Collins Bostak


Archive | 2005

Thermal sensing for integrated circuits

Bruce Doyle; Samuel D. Naffziger; Christopher A. Poirier; James S. Ignowski


Archive | 2003

System and method for measuring current

Christopher J. Fort Collins Bostak; Samuel D. Naffziger; Christopher A. Poirier; Eric S. Fetzer


Archive | 2003

Method and system for calibration of a voltage controlled oscillator (VCO)

Christopher J. Fort Collins Bostak; Samuel D. Naffziger; Christopher A. Poirier; James S. Ignowski


Archive | 2000

Multiple input bit-line detection with phase stealing latch in a memory design

Kevin Liao; Joel D. Lamb; Christopher A. Poirier

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