Samuel D. Naffziger

The implementation of the Itanium 2 microprocessor

This 64-b microprocessor is the second-generation design of the new Itanium architecture, termed explicitly parallel instruction computing (EPIC). The design seeks to extract maximum performance from EPIC by optimizing the memory system and execution resources for a combination of high bandwidth and low latency. This is achieved by tightly coupling microarchitecture choices to innovative circuit designs and the capabilities of the transistors and wires in the 0.18-/spl mu/m bulk Al metal process. The key features of this design are: a short eight-stage pipeline, 11 sustainable issue ports (six integer, four floating point, half-cycle access level-1 caches, 64-GB/s level-2 cache and 3-MB level-3 cache), all integrated on a 421 mm/sup 2/ die. The chip operates at over 1 GHz and is built on significant advances in CMOS circuits and methodologies. After providing an overview of the processor microarchitecture and design, this paper describes a few of these key enabling circuits and design techniques.

Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation

Process variations as a percentage of nominal delay and power consumption are becoming more and more severe with continuing scaling of VLSI technology. The worsening process variation causes increased variability in performance, power, and reliability of VLSI circuits. Thus, performance and power consumption targets obtained during the design phase of VLSI circuits may significantly deviate from that of actual silicon resulting in significant yield losses. Adaptive body bias (ABB) has been shown to be an effective method of postsilicon tuning to reduce variability under the presence of process variation. Post silicon tuning can also be accomplished by using adaptive supply voltage (ASV). This paper compares the effectiveness of ABB and ASV in reducing variability and improving performance and power, and thus, yield.

A sub-nanosecond 0.5 /spl mu/m 64 b adder design

A sub-nanosecond 64 b adder in 0.5 /spl mu/m CMOS forms the basis for the integer and floating point execution units. Integrating dual-rail dynamic CMOS and use of Lings equations, the adder is composed of 7k FETs in 0.246 mm/sup 2/ and performs a full 64 b add, operands to result in <1 ns (7 fanout of 4 inverter delays) under nominal conditions.

A quad-issue out-of-order RISC CPU

A 64 b 4-way superscalar PA-RISC microprocessor system operating from 150-250 MHz combines full out-of-order execution with low-cycle time, to produce >360 specint and >550 specfp. Specialized latching and clock circuits and extensive use of dynamic logic enable high frequency operation. 3.8 M logic transistors are integrated on a 17.68/spl times/19.1 mm/sup 2/ die in 3.3 V 0.5 /spl mu/m CMOS.

The implementation of the next-generation 64 b Itanium/sup TM/ microprocessor

The authors present the 64 bit Itanium/spl trade/ microprocessor, which incorporates over 220M transistors on a 465 mm/sup 2/ die and operates at >1.2 GHz with an 8-stage pipeline in a 0.18 /spl mu/m process. It has three levels of on-chip cache totaling over 3.3 MB providing >32 GB/s bandwidth at each level.