Christopher J. Diorio

Competitive learning with floating-gate circuits

Competitive learning is a general technique for training clustering and classification networks. We have developed an 11-transistor silicon circuit, that we term an automaximizing bump circuit, that uses silicon physics to naturally implement a similarity computation, local adaptation, simultaneous adaptation and computation and nonvolatile storage. This circuit is an ideal building block for constructing competitive-learning networks. We illustrate the adaptive nature of the automaximizing bump in two ways. First, we demonstrate a silicon competitive-learning circuit that clusters one-dimensional (1-D) data. We then illustrate a general architecture based on the automaximizing bump circuit; we show the effectiveness of this architecture, via software simulation, on a general clustering task. We corroborate our analysis with experimental data from circuits fabricated in a 0.35-mum CMOS process.

Design of ultra-low-cost UHF RFID tags for supply chain applications

The availability of inexpensive CMOS technologies that perform well at microwave frequencies has created new opportunities for automated material handling within supply chain management (SCM) that in hindsight, be viewed as revolutionary. This article outlines the system architecture and circuit design considerations that influence the development of radio frequency identification (RFID) tags through a case study involving a high-performance implementation that achieves a throughput of nearly 800 tags/s at a range greater than 10 m. The impact of a novel circuit design approach ideally suited to the power and die area challenges is also discussed. Insights gleaned from first-generation efforts are reviewed as an object lesson in how to make RFID technology for SCM, at a cost measured in pennies per tag, reach its full potential through a generation 2 standard.

A single-transistor silicon synapse

We have developed a new floating-gate silicon MOS transistor for analog learning applications. The memory storage is nonvolatile; hot-electron injection and electron tunneling permit bidirectional memory updates. Because these updates depend on both the stored memory value and the transistor terminal voltages, the synapse can implement a learning function. We have derived a memory-update rule from the physics of the tunneling and injection processes, and have investigated synapse learning in a prototype array. Unlike conventional EEPROM devices, the synapse allows simultaneous memory reading and writing. Synapse transistor arrays can therefore compute both the array output, and local memory updates, in parallel. The synapse is small, and typically is operated at subthreshold current levels; it will permit the development of dense, low-power silicon learning systems.

An autonomous implantable computer for neural recording and stimulation in unrestrained primates

To perform neurobiological experiments on freely behaving primates, we have developed a miniature battery-powered implantable computer capable of recording and stimulating through chronic electrodes in the cortex. The device has: (1) an analog front end with a four-pole bandpass filter (500 Hz-5 kHz), programmable gain and offset nulling; (2) an analog-to-digital converter to sample the data at 11.7 ksps; (3) a programmable microcontroller to discriminate spikes in real time and perform computations; (4) a stimulator to deliver biphasic current pulses of up to 100 muA with variable pulse width and frequency; (5) a 4 Mbit non-volatile memory to store biological data; (6) a 57.6 kbps infrared data link for wireless communications with a hand-held or desktop computer. The device is enclosed in a 5.5 cm x 5 cm x 3 cm titanium casing on the monkeys head along with a 3.3 V lithium battery and an array of cortical electrodes. In in vivo tests, the device was able to record stable cell discharge continuously for time periods of a week or more. After downloading the parameters for recording, stimulation, discrimination, and other computations, the device is capable of operating autonomously, delivering stimuli to one electrode triggered by spikes recorded at a separate site.

Translinear circuits using subthreshold floating-gate MOS transistors

We describe a family of current-mode circuits with multiple inputs and multiple outputs whose output currents are products and/or quotients of powers of the input currents. These circuits are made up of multipleinput floating-gate MOS (FGMOS) transistors operating in the subthreshold regime. The powers are set by capacitor ratios; hence, they can be quite accurate. We analyze the general family of such circuits and present experimental data from several members that we fabricated in a standard 2μm double-poly p-well process through MOSIS.

An autozeroing floating-gate amplifier

We have developed a bandpass floating-gate amplifier that uses tunneling and pFET hot-electron injection to set its dc operating point adaptively. Because the hot-electron injection is an inherent part of the pFETs behavior, we obtain this adaptation with no additional circuitry. Because the gate currents are small, the circuit exhibits a high-pass characteristic with a cutoff frequency less than 1 Hz. The high-frequency cutoff is controlled electronically, as is done in continuous-time filters. We have derived analytical models that completely characterize the amplifier and that are in good agreement with experimental data for a wide range of operating conditions and input waveforms. This autozeroing floating-gate amplifier demonstrates how to use continuous-time floating-gate adaptation in amplifier design.

A high-resolution non-volatile analog memory cell

A 3-transistor non-volatile analog storage cell with 14 bits effective resolution and rail-to-rail buffered voltage output is presented. The memory, which consists of charge stored on a MOS transistor floating gate, is written by means of hot-electron injection and erased by means of gate oxide tunneling. The circuit allows simultaneous memory reading and writing; by writing the memory under feedback control, errors due to oxide mismatch or trapping can be nearly eliminated, Small size and low power consumption make the cell especially attractive for use in analog neural networks. The cell is fabricated in a 2 /spl mu/m n-well silicon Bi-CMOS process available from MOSIS,.

A 300-MS/s 14-bit digital-to-analog converter in logic CMOS

Describes a floating-gate trimmed 14-bit 300-MS/s current-steered digital-to-analog converter (DAC) fabricated in 0.25- and 0.18-/spl mu/m CMOS logic processes. We trim the static integral nonlinearity to /spl plusmn/0.3 least significant bits using analog charge stored on floating-gate pFETs. The DAC occupies 0.44mm/sup 2/ of die area, consumes 53 mW at 250 MHz, allows on-chip electrical trimming, and achieves better than 72-dB spur-free dynamic range at 250 MS/s.

A simulation model for floating-gate MOS synapse transistors

We propose an empirical simulation model for p-channel floating-gate MOS synapse transistors. Since our model requires only a transistor and controlled sources, and does not use the MOSFETs channel potential in its description, we can apply the model in any SPICE circuit simulator. The model parameters derive from simple oxide-current measurements. We present fit parameters from MOSFETs with 70 /spl Aring/ oxides in a 0.35 /spl mu/m process, and verify our model by comparing simulations and measured data from a capacitive-feedback CMOS operational amplifier.

A floating-gate MOS learning array with locally computed weight updates

We have demonstrated on-chip learning in an array of floating-gate MOS synapse transistors. The array comprises one synapse transistor at each node, and normalization circuitry at the row boundaries. The array computes the inner product of a column input vector and a stored weight matrix. The weights are stored as floating-gate charge; they are nonvolatile, but can increase when we apply a row-learn signal. The input and learn signals are digital pulses; column input pulses that are coincident with row-learn pulses cause weight increases at selected synapses. The normalization circuitry forces row synapses to compete for floating-gate charge, bounding the weight values. The array simultaneously exhibits fast computation and slow adaptation: The inner product computes in 10 /spl mu/s, whereas the weight normalization takes minutes to hours.