Todd E. Humes

Design of ultra-low-cost UHF RFID tags for supply chain applications

The availability of inexpensive CMOS technologies that perform well at microwave frequencies has created new opportunities for automated material handling within supply chain management (SCM) that in hindsight, be viewed as revolutionary. This article outlines the system architecture and circuit design considerations that influence the development of radio frequency identification (RFID) tags through a case study involving a high-performance implementation that achieves a throughput of nearly 800 tags/s at a range greater than 10 m. The impact of a novel circuit design approach ideally suited to the power and die area challenges is also discussed. Insights gleaned from first-generation efforts are reviewed as an object lesson in how to make RFID technology for SCM, at a cost measured in pennies per tag, reach its full potential through a generation 2 standard.

A 300-MS/s 14-bit digital-to-analog converter in logic CMOS

Describes a floating-gate trimmed 14-bit 300-MS/s current-steered digital-to-analog converter (DAC) fabricated in 0.25- and 0.18-/spl mu/m CMOS logic processes. We trim the static integral nonlinearity to /spl plusmn/0.3 least significant bits using analog charge stored on floating-gate pFETs. The DAC occupies 0.44mm/sup 2/ of die area, consumes 53 mW at 250 MHz, allows on-chip electrical trimming, and achieves better than 72-dB spur-free dynamic range at 250 MS/s.

Reliability of pFET EEPROM with 70-/spl Aring/ tunnel oxide manufactured in generic logic CMOS Processes

We investigate the reliability of pFET-based EEPROMs with 70-/spl Aring/ tunneling oxides fabricated in standard foundry 0.35-/spl mu/m, 0.25-/spl mu/m, and 0.18-/spl mu/m logic CMOS processes. The floating-gate memory cell uses Fowler-Nordheim tunneling erase and impact-ionization generated hot-electron injection for programming. We show that charge leakage is dominated by the leakage through interlayer dielectrics. We propose a retention model and show the data retention lifetime exceeds 10 years. These results demonstrate the feasibility of producing nonvolatile memory using standard logic processes that have a 70-/spl Aring/ oxide.

A floating-gate trimmed, 14-bit, 250 Ms/s digital-to-analog converter in standard 0.25 /spl mu/m CMOS

We describe a floating-gate trimmed, 14-bit, 250 Ms/s current-steered DAC fabricated in a 0.25 /spl mu/m CMOS logic process. We trim the static INL to /spl plusmn/0.3 LSB using analog charge stored on floating-gate pFETs. The DAC occupies 0.44 mm/sup 2/ of die area, consumes 53 mW at 250 MHz, allows on-chip electrical trimming, and achieves 72 dB SFDR at 250 Ms/s.

Effect of layout orientation on the performance and reliability of high voltage N-LDMOS in standard submicron logic STI CMOS process

An N-LDMOS (N-channel laterally diffused drain MOSFET), fabricated in a standard CMOS process, is used to provide relatively high-voltage (HV/spl sim/12 V) capability without any extra process steps. However, there is very little information available for LDMOS devices with technologies below 0.35 /spl mu/m using STI isolation. In this work, we investigated the typical layout geometry dependence of device drain current leakage, drain breakdown and on-state current characteristics, with devices fabricated in a standard logic 0.18 /spl mu/m and 0.25 /spl mu/m process. Furthermore, for the first time, a dependence on layout orientation and its effect on hot-carrier injection (HCI) reliability are reported.

Measurement of ultralow gate tunneling currents using floating-gate integrator technique

We report for the first time that a gate tunneling current measurement sensitivity better than 3/spl times/10/sup -22/ A has been achieved by using a floating-gate integrator technique. The technique involves monitoring the charge change in the floating-gate integrated with an on-chip op-amp and an on-chip feedback capacitor. We used this technique to study the stress-induced leakage current (SILC) and its cycling dependence of 70 /spl Aring/ oxides in the direct tunneling region at oxide voltage as low as 1.9 V. The technique has been validated through correlation to direct measurement on MOSFET arrays and theoretical calculations. The measured SILC current is modeled with an Inelastic trap-assisted tunneling model.

A low-noise, GaAs/AlGaAs, microwave frequency-synthesizer IC

We have developed a GaAs/AlGaAs frequency-synthesizer IC with a 5.5-GHz feedback divider, a 2-GHz reference divider, a 500-MHz phase-frequency detector, 1-ns charge-pump pulses, and a gain-normalized charge-pump output with /spl plusmn/8-mA peak current and an 18-pA//spl radic/Hz noise floor. The feedback divider allows continuously selectable divide ratios from 12 to 16383, and supports dual-modulus pulse-swallowing fractional synthesis with single-bit control. The reference divider allows continuously selectable divide ratios from 1 to 4095; an optional divide-by-four/five input prescaler extends the divide ratios to 20475. The chip consumes 1 W from +5 and -5.2 V supplies.

Study of stress-induced leakage current and charge loss of nonvolatile memory cell with 70 /spl Aring/ tunnel oxide using floating-gate integrator technique

Techniques for measuring very low tunneling currents are critical for studying gate dielectric properties in MOSFETs, especially charge-loss mechanisms in nonvolatile memory (NVM) devices. Being able to measure stress-induced leakage current (SILC) at the floating gate operating conditions can be used to accurately extract the retention lifetime of floating gate memories. In this work, we utilize a floating-gate integrator technique (capable of resolving currents as low as 3/spl times/10/sup -22/ A) to study the effect of SILC on the charge-retention of logic NVM cells with a 70 /spl Aring/ tunnel oxide, with up to 300 k endurance cycles. The relation between SILC and V/sub ox/ is used to extrapolate the retention lifetime of the memory cell. A conservative estimate of over 10 years retention is found for logic NVM with 70 /spl Aring/ gate tunnel oxides.