Christopher R. Morton

The behavior of digital circuits under substrate noise in a mixed-signal smart-power environment

The behavior of digital circuits in a noisy environment in mixed-signal smart-power systems is described in this paper. Several models and mechanisms explaining the process in which substrate noise affects on-chip digital circuits as well as the noise immunity behavior of digital circuits are presented and discussed. The models and mechanisms are demonstrated by simulations and by extensive test chip-based experimental data.

Substrate coupling in digital circuits in mixed-signal smart-power systems

This paper describes theoretical and experimental data characterizing the sensitivity of nMOS and CMOS digital circuits to substrate coupling in mixed-signal, smart-power systems. The work presented here focuses on the noise effects created by high-power analog circuits and affecting sensitive digital circuits on the same integrated circuit. The sources and mechanism of the noise behavior of such digital circuits are identified and analyzed. The results are obtained primarily from a set of dedicated test circuits specifically designed, fabricated, and evaluated for this work. The conclusions drawn from the theoretical and experimental analyses are used to develop physical and circuit design techniques to mitigate the substrate noise problems. These results provide insight into the noise immunity of digital circuits with respect to substrate coupling.

Placement of Substrate Contacts to Minimize Substrate Noise in Mixed-Signal Integrated Circuits

The placement of substrate contacts in epi and non-epi technologies is analyzed in order to control and reduce the substrate noise amplitude and spreading. The choice of small or large substrate contacts or rings for each of the two major technologies is highlighted. Design guidelines for placing substrate contacts so as to improve the noise immunity of digital circuits in mixed-signal smart-power systems are also presented.

Noise immunity of digital circuits in mixed-signal smart power systems

Experimental data describing circuit and physical design issues that influence the noise immunity of digital latches in mixed-signal smart power circuits are described and discussed. The principal result of this paper is the characterization of the conditions under which substrate noise generated by high power analog circuitry affects digital latches. The experimental data characterize a variety of different noise mitigation techniques for the particular process technology circuit structures, signal/clocking interdependencies, and related conditions.

Placement of substrate contacts to alleviate substrate noise in epi and non-epi technologies

The placement of substrate contacts in epi and non-epi technologies in order to control and reduce the substrate noise amplitude and spreading is analyzed. The choice of small or large substrate contacts or rings for each of the two major technologies are highlighted. Design guidelines for placing substrate contacts particularly appropriate to improving the noise immunity of digital circuits in mixed-signal smart-power systems are also presented.

A comparative study of the behavior of NMOS and CMOS digital circuits under substrate noise

A comparative study of the behavior of NMOS and CMOS digital circuits in terms of the ability to tolerate substrate noise is presented. Theoretical and simulation results are confirmed by experimental data gathered from the analysis of NMOS and CMOS test chips. It is shown that while the noise sensitivity of NMOS digital circuits is influenced by a variety of factors, the primary phenomenon responsible for the noise integrity of the CMOS digital circuits is latch-up.