Chuan-Bi Lin

Module Matching Schemes for Input-Queued Clos-Network Packet Switches

Current schemes for configuration of input-queued three-stage Clos-network (IQC) switches involve port matching and path routing assignment, in that order. The implementation of a scheduler capable of matching thousands of ports in large-size switches is complex. To decrease the scheduler complexity for such switches (e.g., 1024 ports or more), we propose a configuration scheme for IQC switches that hierarchizes the matching process. In a practical scenario our scheme performs routing first and port matching thereafter. This approach reduces the scheduler size and the configuration complexity of IQC switches. We show that the switching performance of the proposed approach using weight-based and weightless selection schemes is high under uniform and nonuniform traffic

Scalable two-stage Clos-network switch and module-first matching

Clos-network switches were proposed as a scalable architecture for the implementation of large-capacity circuit switches. In packet switching, the three-stage Clos-network architecture uses small switches as modules to assemble a switch with large number of ports or aggregated ports with high data rates. However, the configuration complexity of packet Clos-network switches is high as port matching and path routing must be performed. In the majority of the existing schemes, the configuration process performs routing after port-matching is achieved, and thus making port matching expensive in hardware and time complexity for a large number of ports. Here, we reduce the configuration complexity by performing routing first and port matching afterwards in a three-stage Clos-network switch. This approach applies the reduction concept of Clos networks to the matching process. This approach results in a feasible size of schedulers for up to Exabit-capacity switches, an independent configuration of the middle stage modules from port matches, a reduction of the matching communication overhead between different stages, and a release of the switching function to the last-stage modules in a three-stage switch. By using this novel matching scheme, we show that the number of stages of a Clos-network switch can be reduced to two, and we call this the two-stage Clos-network packet switch

Captured-frame matching schemes for scalable input-queued packet switches

Single-stage input-queued (IQ) switches are attractive for implementation of high performance routers because they require no speedup in the used memory. It has been shown that IQ switches can provide 100% throughput under admissible traffic when using maximum-weight matching schemes or iterative maximal-weight matching schemes with a speedup of two or more. These different approaches require either high computation complexity or high memory costs that can make them infeasible. Therefore, there is a need for low-complexity and fast matching schemes that provide high throughput under several admissible traffic patterns, including those with nonuniform distributions, without recurring to speedup nor multiple iterations. In this paper, we introduce the concept of captured frame and apply it to matching schemes. As a result, we propose two weightless matching schemes, one based on round-robin selection, called uFORM, and the other based on random selection, called uFPIM. We analyze the throughput improvement achieved by uFPIM, and show that these matching schemes provide high throughput under a variety of admissible traffic patterns, including those with nonuniform distributions, when using a single iteration and no speedup. Furthermore, we study the scalability of the captured-frame concept in matching schemes for memory-space-memory multiple-stage Clos-network switches, and show the achieved high switching performance and low implementation complexity.

Captured-frame eligibility and round-robin matching for input-queued packet switches

A variety of matching schemes for input-queued (IQ) switches that deliver high throughput under traffic with uniform distributions has been proposed. However, there is a need of matching schemes that provide high throughput under several admissible traffic patterns, including those with nonuniform distributions, while keeping implementation complexity low. In this letter, first, we introduce the captured frame concept for matching schemes in IQ switches. Second, we propose a round-robin based matching scheme, uFORM, which uses the proposed concept for cell matching eligibility. We show via simulation that our matching scheme delivers high throughput under several nonuniform traffic patterns, and retains the high performance under uniform traffic that round-robin matching schemes are known to offer.

Scheme to Measure Packet Processing Time of a Remote Host through Estimation of End-Link Capacity

As transmission speeds increase faster than processing speeds, the packet processing time (PPT) of a host is becoming more significant in the measurement of different network parameters in which packet processing by the host is involved. The PPT of a host is the time elapsed between the arrival of a packet at the data-link layer and the time the packet is processed at the application layer (RFCs 2679 and 2681). To measure the PPT of a host, stamping the times when these two events occur is needed. However, time stamping at the data-link layer may require placing a specialized packet-capture card and the host under test in the same local network. This makes it complex to measure the PPT of remote end hosts. In this paper, we propose a scheme to measure the PPT of an end host connected over a single- or multiple-hop path and without requiring time stamping at the data-link layer. The proposed scheme is based on measuring the capacity of the link connected to the host under test. The scheme was tested on an experimental testbed and in the Internet, over a U.S. inter-state path and an international path between Taiwan and the U.S. We show that the proposed scheme consistently measures PPT of a host.

Frame occupancy-based dispatching schemes for buffered three-stage Clos-network switches

The three-stage Clos-network switch architecture has attractive scalability features that makes it appealing as an alternative for scalable switches. However, scheduling packets in a Clos-network switch is complex. This complexity can be simplified by adding buffers to the first and third stages. By adding these buffers, the scheme used for dispatching packets from the first stage of the switch becomes important. Several dispatching schemes for Clos-network, without internal expansion, that deliver high throughput under uniform traffic model have been proposed. However, there is a need of dispatching schemes that provide high throughput under several admissible traffic patterns, including those with nonuniform distributions, with a small number of matching iterations and without internal expansion. In this paper, we propose two frame-occupancy based dispatching schemes to increase throughput performance in Clos-network switches without using internal expansion. We show that frame-occupancy based schemes deliver high throughput under uniform and nonuniform traffic patterns.

Module-First Matching Schemes for Scalable Input-Queued Space-Space-Space Clos-Network Packet Switches

Clos-network switches were proposed as a scalable architecture for the implementation of large-capacity circuit switches. In packet switching, the three-stage Clos-network architecture uses small switches as modules to assemble a switch with large number of ports or aggregated ports with high data rates. Current schemes for configuration of input-queued three- stage Clos-network (IQC) switches involve port matching and path routing assignment, in that order. The implementation of a scheduler capable of matching thousands of ports in large-size switches is complex because of the large port count. To decrease the scheduler complexity for such switches (e.g., 1024 ports or more), we propose a configuration scheme for IQC switches that hierarchizes the matching process. In a practical scenario our scheme performs routing first and port matching thereafter. This approach applies the reduction concept of Clos networks to the matching process. The application of this approach results in a feasible size of schedulers for up to Exabit-capacity switches, an independent configuration of the middle stage modules from port matches, a reduction of the matching communication overhead between different stages, and a release of the switching function to the last-stage modules in a 3-stage switch. We show that the switching performance of the proposed approach using weight- based and weightless selection schemes is high under uniform and nonuniform traffic.

Frame occupancy-based round-robin matching scheme for input-queued packet switches

The use of virtual output queues (VOQ) in input-queued (IQ) switches can eliminate the head-of-line (HOL) blocking phenomenon, which limits switching performance. An effective matching scheme for IQ switches with VOQ must provide high throughput under admissible traffic patterns while keeping the implementation feasible. This paper proposes a matching scheme for IQ switches that provides high throughput under uniform and a nonuniform traffic pattern, called unbalanced. The proposed matching scheme, FORM, is primarily based on round-robin selection and the captured-frame concept. We show via simulation that this scheme delivers over 99% throughput under unbalanced traffic and retains the high performance under uniform traffic that round-robin matching schemes are known to offer.

An experimental study of small world network model for wireless networks

The concept of small world phenomenon has been observed and applied in many types of networks. This paper evaluates two small-world network models in clustering formation and routing in wireless network. We present simulation of two small world network models, Watts and Stragtzs (WS) and the Newman and Watts (NW) models and evaluate average node degree and path length. We create a test wireless network using standard routing protocols in OPNET to validate the small world phenomenon, evaluate its performance and present research challenges of applying these models for wireless networks. This study provides insights on how wireless networks behave under small world network models with distributed routing protocols.

Minimizing scheduling complexity with a Clos-network space-space-memory (SSM) packet switch

In this paper we propose a three-stage space-space-memory (SSM) Clos-network switch that uses crosspoint buffers in the third-stage modules to eliminate the need for performing multiple iterations in for port matching. We show that the proposed switch not only reduces the configuration complexity of space-space-space (S3) switches but also improves switching performance and relaxes configuration timing. We demonstrate these advantages by comparing the performance of the proposed switch using the weighted module-first no-port (WFM-NP) matching scheme to that of a S3 switch using the original scheduling scheme (with port matching). For higher utilization of the SSM switch, we propose the weighted central-module-link matching (WCMM) scheme. The WCMM scheme rescinds multiple iterations for module matching and yet, it achieves higher performance than the WFM-NP scheme. The advantages of the SSM switch are achieved without memory speedup. The memory addition is a small cost to trade for complexity reduction and performance improvement.