Roberto Rojas-Cessa

CIXB-1: combined input-one-cell-crosspoint buffered switch

Buffered crossbars have been considered as an alternative for non-buffered crossbars to improve switching throughput. The drawback of a buffered crossbar is the memory amount that is proportional to the square of the number of ports (O(N/sup 2/)). This is not the main limitation when the buffer size is kept to a minimum size such that implementation is feasible. For a small buffer size, the number of ports of a switch module is not limited by the memory amount but by the pin count. We propose a novel architecture: a combined input-one-cell-crosspoint buffer crossbar (CIXB-1) with virtual output queues (VOQs) at the inputs and round-robin arbitration. We show that the proposed architecture can provide 100% throughput under uniform traffic. A CIXB-1 offers several advantages for a feasible implementation such as scalability and timing relaxation. With the currently available memory technology, a one-cell-crosspoint buffered switch is feasible for a 32/spl times/32 fabric module.

CIXOB-k: combined input-crosspoint-output buffered packet switch

We propose a novel architecture, a combined input-crosspoint-output buffered (CIXOB-k, where k is the size of the crosspoint buffer) Switch. CIXOB-k architecture provides 100% throughput under uniform and unbalanced traffic. It also provides timing relaxation and scalability. CIXOB-k is based on a switch with combined input-crosspoint buffering (CIXB-k) and round-robin arbitration. CIXB-k has a better performance than a non-buffered crossbar that uses iSLIP arbitration scheme. CIXOB-k uses a small speedup to provide 100% throughput under unbalanced traffic. We analyze the effect of the crosspoint buffer size and the switch size under uniform and unbalanced traffic for CIXB-k. We also describe solutions for relaxing the crosspoint memory amount and scalability for a CIXOB-k switch with a large number of ports.

Concurrent round-robin-based dispatching schemes for Clos-network switches

A Clos-network switch architecture is attractive because of its scalability. Previously proposed implementable dispatching schemes from the first stage to the second stage, such as random dispatching (RD), are not able to achieve high throughput unless the internal bandwidth is expanded. This paper presents two round-robin-based dispatching schemes to overcome the throughput limitation of the RD scheme. First, we introduce a concurrent round-robin dispatching (CRRD) scheme for the Clos-network switch. The CRRD scheme provides high switch throughput without expanding internal bandwidth. CRRD implementation is very simple because only simple round-robin arbiters are adopted. We show via simulation that CRRD achieves 100% throughput under uniform traffic. When the offered load reaches 1.0, the pointers of round-robin arbiters at the first- and second-stage modules are completely desynchronized and contention is avoided. Second, we introduce a concurrent master-slave round-robin dispatching (CMSD) scheme as an improved version of CRRD to make it more scalable. CMSD uses hierarchical round-robin arbitration. We show that CMSD preserves the advantages of CRRD, reduces the scheduling time by 30% or more when arbitration time is significant and has a dramatically reduced number of crosspoints of the interconnection wires between round-robin arbiters in the dispatching scheduler with a ratio of 1/√N, where N is the switch size. This makes CMSD easier to implement than CRRD when the switch size becomes large.

On the combined input-crosspoint buffered switch with round-robin arbitration

Input-buffered switches have been widely considered for implementing feasible packet switches. However, their matching process may not be time-efficient for switches with high-speed ports. Buffered crossbars (BXs) are an alternative to relax timing for packet switches with high-speed ports and to provide high-performance switching. BX switches were originally considered expensive, as the memory amount required in the crosspoints (XPs) is proportional to the square of the number of ports (O(N/sup 2/)). This limitation is now less stringent with the advances on chip-fabrication techniques, and when considering small crosspoint (XP) buffer sizes. In this paper, we study a combined input-crosspoint buffered packet switch, named CIXB, with virtual output queues (VOQs) at the inputs, and arbitration based on round-robin selection. We show that the CIXB switch achieves 100% throughput under uniform traffic, and high performance under nonuniform traffic, using one-cell XP buffer size and no speedup.

A pipeline-based approach for maximal-sized matching scheduling in input-buffered switches

This letter proposes an innovative pipeline-based maximal-sized matching scheduling approach, called PMM, for input-buffered switches. It dramatically relaxes the timing constraint for arbitration with a maximal matching scheme. In the PMM approach, arbitration operates in a pipelined manner. Each subscheduler is allowed to take more than one time slot for its matching. Every time slot, one of them provides the matching result. The subscheduler can adopt a pre-existing efficient round-robin-based maximal matching algorithm. We show that PMM provides 100% throughput under uniform traffic since it preserves a desynchronization effect of the round-robin pointers as in the preexisting algorithm. In addition, PMM maintains fairness for best-effort traffic due to the round-robin-based arbitration.

Round-robin selection with adaptable-size frame in a combined input-crosspoint buffered switch

As an alternative to input-buffered switches, combined input-crosspoint buffered switches relax arbitration timing and provide high-performance switching for packet switches with high-speed ports. It has been shown that these switches, with one-cell crosspoint buffer and round-robin (RR) arbitration at input and output ports, provide 100% throughput under uniform traffic. However, under admissible traffic patterns with nonuniform distributions, only weight-based selection schemes are reported to provide high throughput. We propose an RR based arbitration scheme for a combined input-crosspoint buffered packet switch that provides nearly 100% throughput for several admissible traffic patterns, including uniform and unbalanced traffic, using one-cell crosspoint buffers. The presented scheme uses adaptable-size frames, so that the frame size adapts to the traffic pattern.

Maximum weight matching dispatching scheme in buffered Clos-network packet switches

The scalability of Clos-network switches makes them an alternative to single-stages switches for implementing large-size packet switches. This paper introduces a cell dispatching scheme, called Maximum Weight Matching Dispatching (MWMD) scheme, for buffered Clos-network switches. The MWMD scheme is based on a maximum weight matching algorithm for input-buffered switches. This paper shows that, with request queues in the buffered Clos-network architecture, the MWMD scheme is able to achieve a 100% throughput for independent admissible traffic, without allocating any buffers in the second stage and without expanding the internal bandwidth. As a practical scheme, a maximal oldest-cell-first matching dispatching (MOMD) scheme is also introduced. MOMD shows that using a finite number of iterations in the dispatching scheme, the throughout under unbalanced traffic pattern can be high.

Networking for critical conditions

To enhance the preparedness of federal and state agencies to effectively manage federal or state recovery efforts in response to a broad spectrum of emergencies, we propose a hybrid adaptive network that will adopt currently available off-the-shelf wireless network devices and integrate them quickly into a scalable, reliable, and secure network with a minimum of human intervention for configuration and management. This model will serve as the framework for various rescue missions for securing and distributing critical resources. We investigate different technologies and network strategies and integrate them into the proposed network model to provide seamless support to heterogeneous environments including wireline nodes, ad hoc and sensor network nodes, and network devices based on different standards. In this article we present the network architecture and identify the key technical aspects of its management, security, QoS, and implementation.

Load-balanced combined input-crosspoint buffered packet switch and long round-trip times

The amount of memory in buffered crossbars is proportional to the number of crosspoints, or O(N/sup 2/), where N is the number of ports, and to the crosspoint buffer size, which is defined by the distance between the line cards and the buffered crossbar, to achieve 100% throughput under high-speed data flows. A long distance between these two components can make a buffered crossbar costly to implement. In this letter, we propose a load-balanced combined input-crosspoint buffered packet switch that uses small crosspoint buffers and no speedup. The proposed switch reduces the required size of the crosspoint buffers by a factor of N and keeps the cells in sequence.

Performance of Optical Packet Switches Based on Parametric Wavelength Converters

In an optical packet switch (OPS), input fibers carry multiple wavelengths, each of which carries a packet to one output fiber. As several wavelengths from different inputs could be destined to the same output fiber, one wavelength can be connected and the others remain disconnected, losing the carried packets. Because of the multiple wavelengths available at an output fiber, wavelength conversion in the OPS of the unconnected wavelengths into those available can increase the number of connections. A parametric wavelength converter (PWC) provides multichannel wavelength conversion where wavelengths can be converted to another. A PWC uses a pump wavelength that can be flexibly chosen to define which wavelengths can be converted, defining the so-called wavelength conversion pairs. However, it is unknown which set of pump wavelengths, and therefore the set of connection pairs, should be selected to improve the OPS performance while the number of PWCs in the OPS is reduced. This paper proposes a pump wavelength selection policy for an OPS that uses different pump wavelengths, one for each PWC, within an arbitrarily selected interval. This policy is called a variety-rich (VR) policy. This paper also introduces a non-wavelength-blocking OPS (NWB-OPS) to make full use of PWCs. The switch performance is evaluated through computer simulation. The results show that the proposed policy with different pump wavelengths achieves the highest performance when compared with another of similar complexity. Furthermore, the performance study shows that small sizes of the interval to select a pump wavelength are more beneficial than larger ones.