Chuan Seng Tan

Low temperature CuCu thermo-compression bonding with temporary passivation of self-assembled monolayer and its bond strength enhancement

Abstract Self-assembled monolayer (SAM) of alkane-thiol is formed on copper (Cu) thin layer coated on silicon (Si) wafer with the aim to protect the surface against excessive oxidation during storage in the room ambient. After 3xa0days of storage, the temporary SAM layer is desorbed with in situ anneal in inert ambient to uncover the clean Cu surface. A pair of wafers is bonded at 250xa0°C. Clear evidences of in-plane and out-of-plane Cu grain growth are observed resulting in a wiggling bonding interface. This gives rise to enhancement in shear strength in the bonded Cu Cu layer.

Thermal mitigation using thermal through silicon via (TTSV) in 3-D ICs

Thermal simulation of a stack consists of three IC layers bonded “face up” is performed using finite element modeling. Significant reduction of ~62 °C in maximum chip temperature is predicted by inserting an electrically isolated thermal through silicon via (TTSV) having Cu core and oxide liner shell that extends across IC layers to the substrate. The effects of TTSV dimensions and its extension length in Si substrate are discussed. Additionally, the insertion of a thin layer of graphene at the interface between IC and ILD layers spreads heat more effectively to the TTSV and results in additional cooling.

Mitigating heat dissipation and thermo-mechanical stress challenges in 3-D IC using thermal through silicon via (TTSV)

Thermal modeling of a 3-D IC stack consists of three IC layers bonded back-to-face (or face up) is performed. Significant temperature rise in the top layers is projected with the presence of dielectric isolation films between the IC layers. It is found that by inserting electrically isolated thermal through silicon via (TTSV) having Cu core and oxide liner that extends across the layers to the silicon substrate, significant temperature reduction can be achieved in the maximum temperature. The temperature profile of the 3-D IC stack depends strongly on materials selection for TTSV liner and conductor core, as well as TTSV dimensions. Thermo-mechanical stress induced by TTSV is also discussed and several approaches are proposed to control this stress. Simulation data also suggest that TTSV is useful in mitigating heat dissipation challenges in face-to-face bonding orientation and logic-on-memory stacking.

Achieving low temperature Cu to Cu diffusion bonding with self assembly monolayer (SAM) passivation

In this article, we investigate the feasibility of applying a self assembly monolayer (SAM) onto Cu surface as a passivation layer so as to lower the required temperature during Cu-Cu bonding. Proprietary SAM is applied on Cu layer deposited on Si wafers and studied carefully. The stability of SAM when it is subjected to various exposure times in ambient air and high temperature anneal in inert environment are examined. The contact angle reduces in both cases as compared to freshly coated SAM suggesting that SAM degrades or desorbs over time in room ambient and during high temperature annealing. It is found that the degradation or desorption degree of SAM is inversely proportional to the immersion time in SAM solution. Bonding experiments are carried out to verify the effectiveness of SAM passivation in bonding enhancement at low temperature. The application of SAM passivation layer on Cu layer in order to realize low temperature diffusion bonding is studied. It is found that SAM can effectively passivate Cu surface and readily desorbed prior to bonding. This can provide an ultra-clean Cu surface to achieve diffusion bonding at lower (≪ 300°C) temperature.

Low temperature bump-less Cu-Cu bonding enhancement with self assembled monolayer (SAM) passivation for 3-D integration

Self assembled monolayer (SAM) of alkane-thiol of 6-carbon (1-hexanethiol, C6) chain length is applied on Cu surface (deposited on Si substrate) and examined carefully. Firstly, the ability of SAM adsorption onto Cu surface is confirmed by the sharp rise of water contact angle (CA) on the surface. Next, the thermal stability of SAM when it is stored in different environments is studied. The CA decreases when it is stored in clean room ambient due to partial desorption of the SAM. The desorption behavior of SAM is found to be reversely proportional to the immersion time in SAM solution, whereby longer immersion time shows less desorption. SAM desorption can slowed down significantly if samples are kept at lower temperature (~4°C). Substantial desoprtion of SAM is observed when the samples are annealed above a critical temperature when SAM desorb rapidly from the Cu surface. Surface analysis confirms that Cu surface protected by SAM contains less oxygen. Finally, bonding experiments are performed to validate effectiveness of SAM in tailoring the Cu surface for bonding enhancement at low temperature. Results show that uniform Cu-Cu bond with higher shear strength is obtained as a result of SAM passivation.

Impact of thermal through silicon via (TTSV) on the temperature profile of multi-layer 3-D device stack

IC performance is now predominantly governed by interconnects delay due to smaller wire cross-section, wire pitch and longer lines that traverse across larger chips. These increase the resistance and capacitance hence signal latency of these lines. Material solutions such as Cu/low-κ is no longer able to reduce interconnects delay time as pitch is scaled down further. 3-D ICs with multiple active Si layers is a promising technique to overcome this scaling barrier as it replaces long inter-block global wires with much shorter vertical inter-layer interconnects. Thermal dissipation in present 2-D circuits is known to significantly impact interconnect, performance and device reliability in a negative manner. This problem is expected to be exacerbated further in 3-D ICs as power generated by every silicon layers must now be dissipated through a smaller 3-D chip foot print. This results in a sharp increase in the power density and is a potential show-stopper to 3-D ICs if left unmanaged. In this work, a thorough thermal analysis of a vertically integrated stack consists of three IC layers bonded back to face (or facing up) is carried out using FEM tool. The focus of the present work is to investigate the effectiveness of thermal through silicon via (TTSV) in mitigating heat dissipation challenge at different layers.

Strategy for TSV scaling with consideration on thermo-mechanical stress and acceptable delay

Based on the 2011 ITRS road map, the greater accessibility of higher number of TSVs in a specified area depends on the smarter miniaturization of the interconnect dimension in 3D IC packaging. Scaling down the TSV dimension has an inevitable effect on resistance, capacitance, signal transmission as well as the thermo-mechanical stress. We report that the lowering of the TSV diameter is permissible under thermo-mechanical stress consideration. However, the signal transmission delay explodes rapidly and could be tunable via controlling the liner layer capacitance or/and using alternative filler materials.

Void Density Reduction at the Cu–Cu Bonding Interface by Means of Prebonding Surface Passivation with Self-Assembled Monolayer

A self-assembled monolayer (SAM) of 1-hexanethiol is formed on a copper (Cu) thin layer coated on silicon (Si) wafers with the aim to protect the surface against contamination during storage in room ambient. After 3 days of storage, the SAM is desorbed with an in situ annealing step in inert N 2 ambient to provide a clean Cu surface and a pair of wafers is bonded at 250°C. It is observed with scanning acoustic microscopy that there is a clear reduction in the interfacial void density in the bonded pair compared with the control sample without SAM passivation.

High throughput Cu-Cu bonding by non-thermo-compression method

A non-thermo-compression bonding method by ways of a permanent surface passivation is applied and activated to allow instantaneous Cu-Cu bonding in room ambient hence improving the throughput by at least 30×. This permanent surface finish layer is ultra-thin, CMOS compatible, electrically conductive, resistant to oxidation, does not intermix with Cu, and can be activated readily to achieve fusion bonding (hence not diffusion limited). In this work, clean bump-less Cu surface (100 nm) is coated with a thin passivation layer of 10 nm and protected against ambient oxidation or corrosion. Prior to bonding, the surface is cleaned and activated to achieve a hydrophilic surface with contact angle ~ 10° and RMS roughness of 0.35 nm. A pair of wafers is then brought into intimate contact and bonding is achieved instantaneously via surface energy interaction in clean room ambient. Since the melting temperature of the passivation layer is much higher than the back-end temperature, it is possible to enhance the bond strength further by post-bonding annealing in a batch process. Experimental data show that the mechanical and electrical performance of the Cu-Cu bond is not deteriorated with the application of the permanent passivation layer. The insertion of the thin coating results in a slight increase in sheet resistance from 0.16 ohm/sq (Cu/Cu) to 0.18 ohm/sq (Cu/passivation layer/Cu). I-V measurement across the bonding interface of the non-TCB sample does not reveal clear departure from that of the TCB sample. Four point bending test is performed and the adhesion energy is 14 mJ/m2 (non-TCB) as compared with 12 mJ/m2 for TCB Cu-Cu. The bonding interface is seamless with no void as observed under TEM. This is a major improvement in throughput as compared to thermo-compression bonding as the bonding step is completed in several seconds upon contact without the need for prolonged compression and heating. In addition, bonding is performed in room ambient (25 °C, 1 ATM) with existing tool set. The need of inert bonding chamber is optional. Room temperature bonding is essential to avoid thermal run-out in alignment accuracy as well as better post-bonding thermo-mechanical stress control. Since this non-TCB bonding method is accomplished instantaneously upon contact initialization, it is possible to extend this method to die-on-wafer bonding with reasonable throughput. Die-on-wafer bonding offers greater flexibility in heterogeneous 3D IC stacking with different die size which is not possible by wafer-on-wafer bonding.

Study of Near-Surface Stresses in Silicon Around Through-Silicon Vias at Elevated Temperatures by Raman Spectroscopy and Simulations

The near-surface stress distribution around Cu through-silicon vias (TSVs) was studied by micro-Raman spectroscopy along with finite-element analysis from room temperature to 100°C. Temperature-dependent measurements, along with simulations, revealed that the stresses near TSVs can have two components: 1) the preexisting stress before copper filling; and 2) the coefficients of thermal expansion (CTE)-mismatch-induced stress. The CTE-mismatch-induced stress resulted in a mobility change, and a keep-out zone (KOZ) at elevated temperatures was also estimated, where the KOZ was defined as the region with a mobility change larger than or equal to 10%. Higher temperatures were shown to reduce the CTE-mismatch-induced stress component and resulted in the shrinkage of KOZs in Si. The preexisting stress was shown to be significant in a region equal to or larger than the KOZs induced by the CTE-mismatch-induced stress only and should be characterized and considered in the KOZ determination and the circuit design.