Hong Yu Li

Development of through silicon via (TSV) interposer technology for large die (21×21mm) fine-pitch Cu/low-k FCBGA package

Because of Moores (scaling/integration) law, the Cu/low-k silicon chip is getting bigger, the pin-out is getting higher, and the pitch is getting finer. Thus, the conventional organic buildup substrates cannot support these kinds of silicon chips anymore. To address these needs, Si interposer with TSV has emerged as a good solution to provide high wiring density interconnection, to minimize CTE mismatch to the Cu/low-k chip that is vulnerable to thermal-mechanical stress, and to improve electrical performance due to shorter interconnection from the chip to the substrate. This paper presents the development of TSV interposer technology for a 21×21 mm Cu/low-k test chip on FCBGA package. The Cu/low-k chip is a 65 nm, 9-metal layer chip with 150 µm SnAg bump pitch of total 11,000 I/O, with via chain and daisy chain for interconnect integrity monitoring and reliability testing. The TSV interposer size is 25×25×0.3 mm with CuNiAu as UBM on the top side, and SnAgCu bumps on the underside. The conventional BT substrate size is 45×45 mm with BGA pad pitch of 1 mm and core thickness of 0.8 mm. Mechanical and thermal modeling and simulation for the FCBGA package with TSV interposer have been performed. TSV interposer fabrication processes and assembly process of the large die mounted on TSV interposer with Pb-free micro solder bumps and underfill have been set up. The FCBGA samples have been subjected to moisture sensitivity test and thermal cycling (TC) reliability assessments.

Development of Large Die Fine-Pitch Cu/Low-

The continuous push for smaller bump pitch interconnection in line with smaller Cu/low-k technology nodes demands the substrate technology to support finer interconnection. However, the conventional organic buildup substrate is facing a bottleneck in fine-pitch wiring due to its technology limitation, and the cost of fabricating finer pitch organic substrate is higher. To address these needs, Si interposer with through silicon via (TSV) has emerged as a good solution to provide high wiring density interconnection, and at the same time to minimize coefficient of thermal expansion mismatch to the Cu/low-k chip that is vulnerable to thermal-mechanical stress and improve electrical performance due to shorter interconnection from the chip to the substrate. This paper presents the development of TSV interposer technology for a 21 × 21 mm Cu/low-k test chip on flip chip ball grid array (FCBGA) package. The Cu/low-k chip is a 65-nm nine-metal layer chip with 150-μm SnAg bump pitch of total 11 000 I/O, with via chain and daisy chain for interconnect integrity monitoring and reliability testing. The TSV interposer size is 25 × 25 × 0.3 mm with CuNiAu as under bump metallization on the top side and SnAgCu bumps on the underside. The conventional bismaleimide triazine substrate size is 45 × 45 mm with BGA pad pitch of 1 mm and core thickness of 0.8 mm. Mechanical and thermal modeling and simulation for the FCBGA package with TSV interposer have been performed. TSV interposer fabrication processes and assembly process of the large die mounted on TSV interposer with Pb-free solder bumps and underfill have been set up. The FCBGA samples have passed moisture sensitivity test and thermal cycling reliability testing without failures in underfill delamination and daisy chain resistance measurements.

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In the current 3D integration technology, the control of wafer warp is needed to ensure uniform photolithography, good bonding areas and other major processes that requires flat wafer surface. In this paper, we found out that the wafer warpage was increased with increasing TSV density. The highest wafer warpage was observed after Cu annealing base on step by step warpage monitor. Wafer warpage reduction is achieved by process stage modification.

FCBGA Package With Through Silicon via (TSV) Interposer

The through-silicon-via (TSV) interposer is expected to be the driving vehicle for 2.5-D integrated circuit integration. Although a number of studies have been reported on the thermo-mechanical reliability of TSVs, it remains difficult to justify whether a TSV design or an interposer design is manufacturable or not because we still lack experimental reliability data. This investigation provides important experimental data as well as a series of correlation studies by finite element (FE) simulations. A 2-D analytical solution is also examined to help understand the physics of the problem. Regarding the experimental results, wafer cracking is observed for TSV arrays with large diameters and small pitch-to-diameter ratios after annealing at 300°C. The critical strength to wafer cracking is determined to be 388 MPa from some FE analyses. Through analytical considerations, the influence of TSV diameter on wafer cracking is found to rely on the contributions from the dielectric layer thickness and also the barrier layer thickness. An empirical model for the design of copper-filled TSV interposers is ultimately generated based on the modification of the 2-D solution.

Characterization and management of wafer stress for various pattern densities in 3D integration technology

This paper presents the study on the effect of low k stacked layer, chip pad design structures, and shift pad design TM of a large die size Cu/low kappa (BDtrade) chip for improving assembly and reliability performance on organic buildup substrate FCBGA (FlipChip ball grid array). Bump shear characterization has been performed on the integrity of different stacked layer and pad structure, supported by bump shear modeling analysis. Initial reliability testing was performed on assembled package to identify the best choice of design and finally implemented on the reliability test vehicle for verification. In addition, a potential chip crack problem due to excessive warpage in FCBGA with large die assembly is examined and a simple failure criterion is proposed.

Thermo-Mechanical Design Rules for the Fabrication of TSV Interposers

In this paper, we developed an isotropic wet etching process in a capsule-type bevel etch chamber to reduce a Cu overburden of through Si via (TSV) for less wafer-level warpage with 300 mm wafers. We report the relationship between the wafer-level warpage and the Cu overburden thicknesses controlled by the isotropic wet etching with diluted solution of hydrogen peroxide and sulfuric acid, which is widely used for Cu wet etching. After Cu filling by electroplating, there are humps at the top of the TSVs; therefore, the isotropic wet etching can be considered as a solution to etch away the Cu overburden without any damages on the TSVs. We modified the capsule-type bevel etch chamber to avoid serious attack on TSVs at the center area of the wafer caused by the etchant delivery path. We also adjusted the process parameters to have a controllable Cu etch rate. The etch rate of ~ 0.2 μm/s and the uniformity of ~ 3% were achieved. The overburden was able to be etched up to 3 μm m from the initial Cu overburden. While the Cu overburden decreased during the isotropic wet etching, the TSVs were protected from the etchant because of the humps at the top of the TSVs. After the Cu electroplating, there was a grain size difference between the Cu at TSV and the Cu at field area. Because the microstructural difference caused a galvanic corrosion during the wet etching, the etch rate of the adjacent Cu around TSV was faster than the Cu at any other area. That resulted in exposure of dielectric layer at the adjacent area around TSVs when the Cu overburden was etched heavily. It may be another protection mechanism of TSV during the isotropic wet etching. The wafer-level warpage of the wafer with the Cu overburden etched up to 3 μm after the annealing decreased by 50% from that of the wafer with the initial Cu overburden. The wafer-level warpage exhibited a linear relationship with the Cu overburden thickness controlled by the isotropic wet etching.

Impact of packaging design on reliability of large die Cu/low-κ (BD) interconnect

The effects of temporary bonding processes on thin wafer handling were investigated. Backside dielectric curing process was found to be a critical process for the void formation in the thin wafer handling which was confirmed by scanning acoustic microscope and by thermo-gravimetric analyzer out-gassing analysis. The effects of voids on back-side wafer processes were discussed. Finally, 3-D through silicon via integration with thin wafer handling (50 μm in thickness) was demonstrated with selected dielectric passivation material and temporary bonding adhesives.

Relationship Between Wafer-Level Warpage and Cu Overburden Thickness Controlled by Isotropic Wet Etching for Through Si Vias

This paper presents the study on the effect of low-κ stacked layer, chip pad design structures, and shift pad design of a large die size Cu/low-κ chip for improving assembly and reliability performance on organic buildup substrate flip chip ball grid array (FCBGA). Bump shear characterization has been performed on the integrity of different stacked layer and pad structure, supported by bump shear modeling analysis. Initial reliability testing was performed on assembled package to identify the best choice of design and finally implemented on the reliability test vehicle for verification. In addition, a potential chip crack problem due to excessive warpage in FCBGA with large die assembly is examined and a simple failure criterion is proposed.

Compatibility of Dielectric Passivation and Temporary Bonding Materials for Thin Wafer Handling in 3-D TSV Integration

Under bump metallization (UBM)-Al delamination is a high-value chip-package interaction reliability problem in flip-chip Cu pillar packaging. We devised a test vehicle for quick reliability assessment. We demonstrate that preclean is a critical step to ensure reliable UBM-Al adhesion and achieve bump shear strength >12 g/mil2 for 15-μm polymer opening. Key parameters affecting bump shear strength, such as UBM critical dimension (CD), polyimide (PI) CD, SiN CD, and PI thickness, were reviewed from both simulation and experimental standpoints and good agreement was achieved between the two. Based on the observed failure mode, a 1-D model was also proposed to correctly predict the experimental trend. Optimum design rules for Cu pillar were outlined. Chip-substrate assembly was demonstrated on 80-μm bump pitch with staggered bump configuration using mass reflow. Progressive thermal cycling was performed to evaluate package performance. Failure mode was found to be solder crack, verifying the improvement in UBM-Al adhesion.