Chuanyun Wang

Common-Mode EMI Study and Reduction Technique for the Interleaved Multichannel PFC Converter

Interleaved multichannel power factor correction (PFC) converter is very popular today because of its ability to reduce input and output current ripples. In this paper, the common-mode (CM) electromagnetic interference noise emission model of the multichannel PFC converter is studied. A balance technique is introduced to reduce CM noise emission. To improve the high-frequency balance, a novel topology with coupled-inductor structure is proposed. Its CM noise model is derived and balance condition for minimizing CM noise is calculated. Effects of phase shift and channel shedding on this solution are also studied. The proposed topology has effectively reduced CM noise under any phase shift and channel shedding conditions. A two-channel PFC converter is built to verify the proposed balance technique. Experimental results show that CM noise can be reduced up to 20 dB between 150 kHz and 7 MHz.

Power architecture design with improved system efficiency, EMI and power density

The optimized design of power architecture is discussed in this paper. The paper first discusses the asymmetrical interleaved multi-channel PFC technique and its benefits to system power density and the reduction of differential mode noise. A balance technique is then proposed to minimize the common mode noise of asymmetrical interleaved multi-channel PFC. Greatly reduced EMI leads to the size reduction of EMI filters. System power density is therefore improved. For DC/DC stage, a 1 MHz, LLC resonant converter with novel synchronous rectifier is proposed to reduce body diode conduction time. Both conduction loss and reverse recovery loss can be reduced. The whole systems efficiency, EMI and power density can be greatly improved by applying the techniques proposed in this paper.

EMI Study for the Interleaved Multi-Channel PFC

For high power application the interleaved multichannel PFC is becoming more and more popular. It can effectively reduce the input ripple current due to the ripple cancellation effect. It is generally believed that the reduced input ripple current will lower down the DM EMI noise magnitude, which will make the DM Alter smaller. However, for most of todays PFC, running in the frequency range of 75 kHz ~ 150 kHz, the conventional 2-channel interleaving technique cannot help to reduce the EMI filter size at all. In this switching frequency range, the EMI filter design is based on the 2nd order harmonic, which cannot be reduced by the conventional interleaving. In this paper, a 2-channel PFC operating with 90 degree phase shift is introduced. It can cancel the 2nd order harmonic and reduce the 3rd order harmonic, and the EMI filter size can be reduced. This novel interleaving strategy can be further extended to other switching frequency range and other multi-channel interleaved PFC.

Light load efficiency improvement for multi-channel PFC

With the fast growing information technologies, AC-DC front-end power supply design is facing extremely tough challenges due to the continuously increasing power density and efficiency requirement. For the PFC stage, how to reduce the boost inductor and the EMI filter size without compromising the efficiency is the key to meet the challenges. Lots of techniques has been studied and proposed during the last several years. Among these techniques, multi-channel interleaving is a quite promising one. By staggering the channels at uniform intervals, multichannel interleaved PFC can reduce the EMI filter size significantly due to the ripple cancellation effect. In addition, the interleaving multi-channel configuration makes it possible to implement the phase-shedding to improve the PFC light load efficiency. Today, the power supply industry is spending tremendous effort on improving the PFC light efficiency due to the economic reasons and environmental concerns. By decreasing the number of active channels according to the load, the PFC light load efficiency can be optimized. In this paper, the phase-shedding control is proposed to improve the PFC light load efficiency and the issues on the EMI filter design are investigated. To improve the light load efficiency without compromising the EMI filter size, the asymmetrical phase angle control strategy is proposed, and is verified and demonstrated by the experimental results.

Asymmetrical interleaving strategy for multi-channel PFC

The continuously increasing efficiency and power density requirement of the AC-DC front-end converter posed a big challenge for todays power factor correction (PFC) circuit design. The multi-channel interleaved PFC is a promising candidate to achieve the goals. In this paper, the multi-channel interleaving impact on the EMI filter design and the output capacitor life time is investigated. By properly choosing the interleaving channel number and the switching frequency, the EMI filter size and cost can be effectively reduced. Further more; multi-channel PFC with asymmetrical interleaving strategy is introduced, and the additional benefit on the EMI filter is identified. At the output side, different interleaving schemes impact on the output capacitor ripple cancellation effect is also investigated and compared.

New Architecture for MHz Switching Frequency PFC

In this paper, the concept of high frequency operation to shrink the EMI filter and inductor size in the PFC circuit is demonstrated. A 600 kHz single switch CCM boost PFC with 92% full load efficiency at 90 VAC input is developed with the Infineon newly developed CoolMOS and SiC diode devices. Both the EMI filter and the inductor size are greatly reduced. Further more, a new two-stage PFC architecture is introduced. This enables the PFC to run at 1 MHz with 92.8% full load efficiency. At such high operating frequency, the EMI filter and inductor size is further reduced. For the second stage in this structure, a high efficiency, and high power density voltage doubler is proposed. The measured full load efficiency of the voltage doubler prototype is 99%. Interleaving multi-phase high frequency PFC architecture is also introduced. The ability to reduce the EMI filter size by increase the EMI noise frequency is discussed and demonstrated.

Light load efficiency improvement for PFC

With the fast growing information technologies, high efficiency AC-DC front-end power supplies are becoming more and more desired in all kinds of distributed power system applications due to the energy conservation consideration. For the power factor correction (PFC) stage, the conventional constant frequency average current mode control has very low efficiency at light load due to high switching frequency related loss. The constant on-time control for PFC features the automatic reduction of switching frequency at light load, resulting improved light load efficiency. However, lower heavy load efficiency of the constant on-time control is observed because of very high frequency at Continuous Conduction Mode (CCM). By carefully comparing the on-time and frequency profiles between constant on-time and constant frequency control, a novel adaptive on-time control is proposed to improve the light load efficiency without sacrificing the heavy load efficiency. The performance of the adaptive on-time control is verified by experiment.

A high power-density, high efficiency front-end converter for capacitor charging applications

This paper introduces a high power-density, high-efficiency isolated full-bridge boost converter, which is used for the front-end converter of a capacitor charger. The design equations, design considerations and practical trade-offs for the converter power stage are summarized. In addition, by fully taking advantage of the pulsed load profile, a transformer design using a high-saturation flux density material is introduced to maximize the power density. The principle of operation for the converter is analyzed and verified on a 15 kW, 100 kHz front-end converter prototype.

A high power density high voltage distributed power system for pulse power applications

In this paper, a high-density high-voltage distributed power system for pulse power applications is designed and implemented. Different topologies are evaluated for two power stages. According to pulse load condition, system power density is optimized through the tradeoff between power loss and magnetic component size. High power density and high efficiency are verified by the experimental result

Control and simulation for hybrid solid oxide fuel cell power systems

Hybrid solid oxide fuel cell (SOFC)-gas turbine (GT) power system provides a promising solution for powering the future aircraft. This electrical power generation technology can achieve both the high efficiency and very low emission. However, two independent energy sources in the system, SOFC and GT, require more dedicated power management strategy. A novel power tracking control method is proposed in this paper to address the issue of power partitioning between two energy sources. In order to analysis and verify the control strategy in the hybrid SOFC system, a detailed system simulation platform is developed. The simulation results demonstrate that the power tracking control can effectively control the load power distribution between two channels.