Chuanzhao Yu

Analysis and modeling of LC oscillator reliability

In this paper, MOS device degradations due to hot carrier and gate oxide breakdown are shown experimentally, and their effects on the NMOS LC oscillator have been evaluated analytically and through SpectreRF simulation. The reduction in transconductance of the differential pair transistors may cause the oscillation to cease. The amplitude of oscillation reduces as the equivalent tank resistance decreases due to the breakdown effect on the MOS varactor. The reduction of amplitude reduces the tank capacitances, and therefore shifts the frequency of oscillation and increases the oscillator phase noise. The tank amplitude of the oscillator is derived analytically. A closed-form expression for the average capacitance of the varactor that accounts for large-signal effects is presented. Finally, a set of guidelines to design an LC oscillator in reliability is presented.

PMOS breakdown effects on digital circuits Modeling and analysis.

Abstract The degradations in the pMOS device due to gate oxide breakdown introduced by voltage stress were investigated experimentally. The stress-induced shifts in gate leakage and I–V characteristics were presented. A combined Verilog-A and sub-circuit model was first time introduced and employed to simulate the pMOS breakdown behaviors. The Verilog-A model can accurately simulate the power law characteristics of breakdown gate leakage current with a fractional coefficient. With the developed model, the simulated results and the measurements have good agreements. The traditional logic circuits, such as the inverter and the latch, have been investigated through Cadence simulations with the improved models. The latch suffers from the gate oxide breakdown significantly. The NULL Convention Logic (NCL) circuit has also been examined and analyzed systematically. The results showed substitute degradations due to the pMOS gate oxide breakdown.

Study of Electrical Stress Effect on SiGe HBT Low-Noise Amplifier Performance by Simulation

This paper investigates the hot-carrier-induced performance degradation in a cascode low-noise amplifier using SiGe heterojunction bipolar transistors. Changes in device characteristics due to accelerated hot-carrier stress are examined experimentally. The vertical bipolar inter-company (VBIC) model parameters extracted from measured device data before and after stress are used in Cadence SpectreRF simulation to evaluate the circuit performance degradation

Analysis and modeling of LNA circuit reliability

This paper systematically investigates the hot carrier (HC) and soft breakdown (SBD) effects on different low noise amplifier (LNA) circuit configurations. After the MOSFET device RF parameter degradations due to HC and SBD effects are experimentally evaluated, the HC and SBD induced performance degradations of three LNA configurations are evaluated for 0.16 /spl mu/m CMOS technology. The applications include Bluetooth and wireless LAN systems. The analytical equations for noise figure are derived, and the degradation models are also obtained. This work can help LNA designers to design more reliable LNA circuits.

Study of performance degradations in DC-DC converter due to hot carrier stress by simulation

Abstract The hot carrier effects on the 0.25 μm high voltage LDMOS has been examined by the accelerated stress experiment. Although the model parameters changed slightly, the switching performances degraded significantly, which have been simulated with the compact models extracted from the test devices by ICCAP. A full bridge DC-DC converter with the compact models was proposed in Cadence SpectreRF. The simulated results show that the efficiency of the full bridge DC-DC converter degraded significantly due to the hot carrier effects.

Hot carrier and soft breakdown effects on LNA performance for ultra wideband communications

This paper systematically investigates the hot carrier (HC) and soft breakdown (SBD) effects on CMOS low noise amplifier (LNA) for the ultra wide-band (UWB) of 3.1 to 7 GHz. After the MOSFET device RF parameter degradations due to HC and SBD effects are experimentally extracted, the HC and SBD induced performance degradations of the LNA for UWB are evaluated for 0.16 μm CMOS technology, including s-parameters, noise figure, and stability factor. This work can help RF designers to design more reliable LNA circuits for upcoming UWB applications.

Dynamic voltage stress effects on nMOS varactor

The degradations in the nMOS device due to high-frequency (900 MHz) dynamic stress are shown experimentally. The stress-induced shifts in DC and larger-signal C-V characteristics are presented. Although the high-frequency stress-induced degradations are much smaller than DC stress, the effects on C-V curves and quality factor cannot be neglected. An nMOS LC oscillator, wherein the varactor is operated under the same dynamic bias conditions as in the stress experiment, has been evaluated through Cadence Spectre simulation. The performance of the LC oscillator degrades significantly due to the dynamic stress.

Voltage stress-induced hot carrier effects on SiGe HBT VCO

This paper presents the hot carrier (HC) induced performance degradation in a 10 GHz voltage controlled oscillator (VCO) with SiGe heterojunction bipolar transistors (HBTs). SiGe device characteristics due to HC stress are examined experimentally. The vertical bipolar inter-company (VBIC) model parameters extracted from measured data are used in Cadence SpectreRF simulation to verify the HC effect on the VCO. The VCO shows significant vulnerability to hot carriers.

Dynamic stress-induced high-frequency noise degradations in nMOSFETs

Device parameter shifts in nMOSFETs subject to inverter-like dynamic voltage stress are examined experimentally. Model equations to relate high-frequency noise to device parameters are given. Dynamic stress-induced degradations in high-frequency noise performance of 0.16 μm nMOSFETs are investigated. Good agreement between the analytical predictions and experimental data is obtained. Noise performance of a Gilbert mixer is evaluated using Cadence SpectreRF simulation with the measured device model parameters.

RF reliability of MOSFETs subject to electrical stress

The impact of gate and drain voltage stress on the analog performance of MOSFETs at RF frequencies was studied systematically. 0.16-/spl mu/m NMOSFETs have been evaluated experimental to examine the RF performance metrics such as cutoff frequency, linearity, noise figure, and 1/f noise. A methodology is presented to study the reliability in MOSFETs subject to stress. Both circuit simulation and measurement data are employed to prove the finding and methodology.