Jiann S. Yuan

Optimization of NULL convention self-timed circuits

Self-timed logic design methods are developed using Threshold Combinational Reduction (TCR) within the NULL Convention Logic (NCL) paradigm. NCL logic functions are realized using 27 distinct transistor networks implementing the set of all functions of four or fewer variables, thus facilitating a variety of gate-level optimizations. TCR optimizations are formalized for NCL and then assessed by comparing levels of gate delays, gate counts, transistor counts, and power utilization of the resulting designs. The methods are illustrated to produce (1) fundamental logic functions that are 2.2-2.3 times faster and require 40-45% fewer transistors than conventional canonical designs, (2) a Full Adder with reduced critical path delay and transistor count over various alternative gate-level synthesis approaches, resulting in a circuit with at least 48% fewer transistors, half as many gate delays to generate the carry output, and the same number of gate delays to generate the sum output, as its nearest competitors, and (3) time, space, and power optimized increment circuits for a 4-bit up-counter, resulting in a throughput-optimized design that is 14% and 82% faster than area- and power-optimized designs, respectively, an area-optimized design that requires 22% and 42% fewer transistors than the speed- and power-optimized designs, respectively, and a power-optimized design that dissipates 63% and 42% less power than the speed- and area-optimized designs, respectively. Results demonstrate support for a variety of optimizations utilizing conventional Boolean minimization followed by table-driven gate substitutions, providing for an NCL design method that is readily automatable.

Delay-insensitive gate-level pipelining

Abstract Gate-level pipelining (GLP) techniques are developed to design throughput-optimal delay-insensitive digital systems using NULL convention logic (NCL). Pipelined NCL systems consists of combinational , registration , and completion circuits implemented using threshold gates equipped with hysteresis behavior. NCL combinational circuits provide the desired processing behavior between asynchronous registers that regulate wavefront propagation. NCL completion logic detects completed DATA or NULL output sets from each register stage. GLP techniques cascade registration and completion elements to systematically partition a combinational circuit and allow controlled overlapping of input wavefronts. Both full-word and bit-wise completion strategies are applied progressively to select the optimal size grouping of operand and output data bits. To illustrate the methodology, GLP is applied to a case study of a 4-bit×4-bit unsigned multiplier, yielding a speedup of 2.25 over the non-pipelined version, while maintaining delay insensitivity.

Design of Asynchronous Circuits for High Soft Error Tolerance in Deep Submicrometer CMOS Circuits

As the devices are scaling down, the combinational logic will become susceptible to soft errors. The conventional soft error tolerant methods for soft errors on combinational logic do not provide enough high soft error tolerant capability with reasonably small performance penalty. This paper investigates the feasibility of designing quasi-delay insensitive (QDI) asynchronous circuits for high soft error tolerance. We analyze the behavior of null convention logic (NCL) circuits in the presence of particle strikes, and propose an asynchronous pipeline for soft-error correction and a novel technique to improve the robustness of threshold gates, which are basic components in NCL, against particle strikes by using Schmitt trigger circuit and resizing the feedback transistor. Experimental results show that the proposed threshold gates do not generate soft errors under the strike of a particle within a certain energy range if a proper transistor size is applied. The penalties, such as delay and power consumption, are also presented.

NULL Convention multiply and accumulate unit with conditional rounding, scaling, and saturation

Approaches for maximizing throughput of self-timed multiply-accumulate units (MACs) are developed and assessed using the NULL convention logic paradigm. In this class of self-timed circuits, the functional correctness is independent of any delays in circuit elements, through circuit construction, and independent of any wire delays, through the isochronic fork assumption [1,2], where wire delays are assumed to be much less than gate delays. Therefore self-timed circuits provide distinct advantages for System-on-a-Chip applications.First, a number of alternative MAC algorithms are compared and contrasted in terms of throughput and area to determine which approach will yield the maximum throughput with the least area. It was determined that two algorithms that meet these criteria well are the Modified Baugh-Wooley and Modified Booth2 algorithms. Dual-rail non-pipelined versions of these algorithms were first designed using the threshold combinational reduction method [3]. The non-pipelined designs were then optimized for throughput using the gate-level pipelining method [4]. Finally, each design was simulated using Synopsys to quantify the advantage of the dual-rail pipelined Modified Baugh-Wooley MAC, which yielded a speedup of 2.5 over its initial non-pipelined version. This design also required 20% fewer gates than the dual-rail pipelined Modified Booth2 MAC that had the same throughput. The resulting design employs a three-stage feed-forward multiply pipeline connected to a four-stage feedback multifunctional loop to perform a 72 + 32 × 32 MAC in 12.7 ns on average using a 0.25 µm CMOS process at 3.3 V, thus outperforming other delay-insensitive/self-timed MACs in the literature.

Reliability and failure mechanisms of lateral MOSFETs in synchronous DC-DC buck converter

This paper present an evaluation of the reliability of LDMOS transistors in synchronous DC-DC buck converter using physical-based mixed device and circuit simulation. It is observed that impact ionization, lower temperature, and radiation degrade power MOSFET performances and could lead to potential failure if heavy ions strike the converter at critical time during switching.

PMOS breakdown effects on digital circuits Modeling and analysis.

Abstract The degradations in the pMOS device due to gate oxide breakdown introduced by voltage stress were investigated experimentally. The stress-induced shifts in gate leakage and I–V characteristics were presented. A combined Verilog-A and sub-circuit model was first time introduced and employed to simulate the pMOS breakdown behaviors. The Verilog-A model can accurately simulate the power law characteristics of breakdown gate leakage current with a fractional coefficient. With the developed model, the simulated results and the measurements have good agreements. The traditional logic circuits, such as the inverter and the latch, have been investigated through Cadence simulations with the improved models. The latch suffers from the gate oxide breakdown significantly. The NULL Convention Logic (NCL) circuit has also been examined and analyzed systematically. The results showed substitute degradations due to the pMOS gate oxide breakdown.

Supply voltage scalable system design using self-timed circuits

Supply voltage scalable system design for low power is investigated using self-timed circuits in this paper. Two architectures are proposed to achieve supply voltage scalability, for preserved quality and energy-quality tradeoff respectively, In the first architecture, the supply-voltage automatically tracks the input data rate of the data path so that the supply-voltage can be kept as small as possible while maintaining the speed requirement and processing quality. In the second one, further energy saving is achieved at the cost of signal-noise-ratio loss in digital signal processing when an ultra-low supply voltage is applied. Cadence simulation shows the effectiveness for both architectures. More than 40% to 70% power can be saved by introducing -150 to -10 dB error in a case study: speech signal processing.

Enhanced techniques for current balanced logic in mixed-signal ICs

In this paper, dual-V/sub T/ and negative feedback are proposed to reduce the noise of the current-balanced logic for mixed-signal ICs. Based on the circuit analysis and SPICE simulation, the dual-V/sub T/ technique shows advantages over the conventional current-balanced logic design in gate area, delay, power dissipation, and switching noise. The negative feedback further reduces the noise spike.

High throughput power-aware FIR filter design based on fine-grain pipelining multipliers and adders

In regular FIR structure, by pipelining the multipliers one can improve the throughput. But as with the growth of operand word length, the delay in addition process becomes another important constraint. In this paper, a novel fine-grain pipelining scheme for high throughput FIR is proposed. By pipelining multipliers and adders, very high throughput can be achieved. 2-dimensional pipeline gating technique is used to make the designed FIR power aware of the precision of the operands. The average power dissipation and latency are both significantly reduced with changing of input precisions.

Examination of hot carrier effects of the AlGaAs/InGaAs pHEMT through device simulation

Abstract A unified study on the hot carrier reliability and the effect of temperature on the pseudomorphic high electron mobility transistor (pHEMT) is carried out through device simulation and physical analyses. Device cross sections are evaluated at various biasings to examine the physical behavior. An accelerated DC stress regime and normal operation regime are examined through TCAD. Output characteristics are shown along with stress mechanisms within the device. This includes impact ionization, hole and electron currents, and heating effects. While these effects have been reported previously, this work provides them in a complete visual and concise manner. Lastly, a means of simulating a pHEMT post-stress is introduced. This approach accounts for the activation of dopants near the channel. Post-stress simulation results of DC and RF performance parameters ( I DS , g m f T , f max , S 21 ) are then investigated. Simulation shows that the effect of stress is highly dependent on the chosen bias point used after stress.