Chul Hi Han

Surface micromachined solenoid on-Si and on-glass inductors for RF applications

RF performance of surface micromachined solenoid on-chip inductors fabricated on a standard silicon substrate (10 /spl Omega//spl middot/cm) has been investigated and the results are compared with the same inductors on glass. The solenoid inductor on Si with a 15-/spl mu/m thick insulating layer achieves peak quality (Q-) factor of 16.7 at 2.4 GHz with inductance of 2.67 nH. This peak Q-factor is about two-thirds of that of the same inductor fabricated on glass. The highest performance has been obtained from the narrowest-pitched on-glass inductor, which shows inductance of 2.3 nH, peak Q-factor of 25.1 at 8.4 GHz, and spatial inductance density of 30 nH/mm/sup 2/. Both on-Si and on-glass inductors have been modeled by lumped circuits, and the geometrical dependence of the inductance and Q-factor have been investigated as well.

Monolithic Fabrication of Electroplated Solenoid Inductors Using Three-Dimensional Photolithography of a Thick Photoresist

A novel and high-yield fabrication process has been devised for monolithic integration of solenoid inductors. In order to simplify the fabrication steps, we decompose the solenoid inductor into two parts, bottom conductor lines and air bridges. The air bridge is formed as a single body during a single electroplating step. This single-step fabrication of the air bridges is possible by forming a three-dimensional (3D) photoresist mold using multiple exposures with varying exposure depths, followed by a single development step, which realizes the 3D latent image of the unexposed volume in the photoresist. We have successfully fabricated solenoid inductors with and without a magnetic core using this process. This process is easy and simple, so that one can significantly improve the fabrication yield over that achieved by conventional methods. Also, this process has good compatibility with the integrated circuit (IC) process owing to a low process temperature (<120°C) and the monolithic feature.

Monolithic integration of 3-D electroplated microstructures with unlimited number of levels using planarization with a sacrificial metallic mold (PSMM)

A new monolithic integration method for 3-D electroplated microstructures of unlimited number of levels has been developed using unique planarization with a sacrificial metallic mold (PSMM). Contrary to the conventional electroplating mold of photoresist or polyimide, the sacrificial metallic mold (SMM) is used for multiple functions: a sacrificial layer, a planarization layer, and a seed layer for the next-level electroplating as well. We have successfully demonstrated various three-level metallic microstructures, such as levitated on-chip inductors, micro-bridges, micro-cantilevers, and micro-mirrors. The RF performance of the fabricated inductor has shown excellent results of 5 nH, Q-factor of 50 at 5 GHz on glass. This method is very simple, highly adaptable, and IC-compatible, so that it can be used as a versatile tool to integrate various 3-D metallic microstructures in multiple levels.

Leakage mechanisms in the heavily doped gated diode structures

A leakage current model is presented which shows very good agreement with reported experimental results on gated diode structures with contemporary ULSI dimensions. The leakage current is modeled as the Shockley-Read-Hall generation current, enhanced by the Poole-Frenkel effect and trap-assisted tunneling. The model shows very good agreement on gate voltage, temperature, and oxide thickness dependence for the normal operating voltage range. It is found from the model that the doping range from 2*10/sup 18/ to 1*10/sup 19/ cm/sup -3/ gives the most significant degradation to the leakage characteristics in trench-type DRAM cells and the drain of MOSFETs. >

Novel two-step baking process for high-aspect-ratio photolithography with conventional positive thick photoresist

We have developed a novel two-step baking process to achieve high-aspect-ratios in UV photolithography with a conventional positive thick photoresist. We newly report high-aspect-ratio (greater than 10:1) results in a single coated 91 micrometer- thick photoresist AZ9262, which was introduced Hoechst at SPIE in 1996. From extensive experiments, we improved the aspect ratio by minimum exposure, diluted development, reabsorption of sufficient water before exposure, and especially by extended and effective soft bake in two steps. In the optimum two-step baking, first the baking is performed at an intermediate temperature in a forced convection oven for hours to evaporate large amounts of solvent. Second, the photoresist is heat-treated at an elevated temperature on an air-gapped hotplate with cover for minutes to enhance aspect ratios. The reason for this improvement has been studied based on the photochemical process of the DNQ/novolac-type positive photoresist. Using this two-step baking, we have obtained lines of 4.4 micrometer-wide bottom in a single coated 91 micrometer-thick photoresist (aspect ratio: 20). The line width in the mask was 8.9 micrometer, and hence 2.2 micrometer undercut was observed.

Low-Temperature Plasma Etching of Copper Films Using Ultraviolet Irradiation

Inductively coupled plasma etching of copper under ultraviolet (UV) irradiation is proposed. We achieved an etch rate of about 300 nm/min at room temperature using Cl2/N2 (or Cl2/Ar) gas mixture. UV light irradiation lowers the activation energy of copper etching from 1.6 eV to 0.12 eV and enhances CuCl desorption, which makes it possible to etch copper at low temperatures. The etch rate increases almost linearly with increasing UV light intensity, and then saturates at high UV intensity. It is concluded that the etching process is not a simple thermal process, but a kind of photodesorption of CuCl due to ultraviolet irradiation. This etching method will bring us closer to high-resolution copper metallization.

Novel and High-Yield Fabrication of Electroplated 3D Micro-Coils for MEMS and Microelectronics

A novel and high-yield process is presented to fabricate electroplated 3D micro-coils for MEMS and microelectronics. The 3D Solenoid-type Integrated Inductor (SI2) is decomposed into two parts, bottom conductor lines and air bridges. The bridges are formed by only one electroplating step. This single-step fabrication of the electroplated air bridges is possible by forming the 3D photoresist mold with a Multi-Exposure and Single Development method (MESD). We have successfully demonstrated 3D micro-coils with or without a core. This method is so easy and simple that we can dramatically improve the fabrication yield, which is the hardest obstacle in the various 3D micro-coil fabrication methods. Also, this method has good IC process compatibility owing to low process temperature and the monolithic feature.

Short Channel Effects in N- and P-Channel Polycrystalline Silicon Thin Film Transistors with Very Thin Electron Cyclotron Resonance N2O-Plasma Gate Dielectric

To suppress short-channel effects in polysilicon thin film transistors, very thin electron cyclotron resonance (ECR) N2O-plasma gate oxide is investigated experimentally. ECR N2O-plasma oxidation incorporates nitrogen atoms at the interface and forms strong Si≡N bonds. With the ECR N2O-plasma oxide of 12 nm thickness, short-channel effects can be almost eliminated for n-channel (p-channel) thin film transistors of 3 µm (1 µm) gate length. It is inferred that reduction of defects by N2O-plasma passivation and strong Si≡N bonds lead to good immunity to impact ionization, resulting in the suppression of short-channel effects.

Uniform and simultaneous fabrication of high-precision and high-density orifice, channel, and reservoirs for ink-jet printheads

We have fabricated a unified Orifice Plate Assembly (OPA) for high-resolution inkjet printheads, which has orifices, ink flow channels, and reservoirs three-dimensionally in a single body, using single-step 3D photolithography followed by single-step electroplating. These three components are the core in inkjet printheads because they determine almost all of ink fluidics, especially the size and trajectory of an ink drop. Therefore, for high-resolution beyond 600 dpi, a unified and high-precision orifice plate assembly is strongly needed. By newly devised 3D patterning technique, namely Multi- Exposure and Single Development (MESD), we form the 3D photoresist mold for the unified OPA. Once the 3D unified OPA mold is fabricated, nickel electroplating is performed on it until the roof of the channel molds is fully covered by the overplated Ni, and until all the plating fronts around orifices in the entire wafer converge to their salient orifice molds. This converging margin in the electroplating step, which is originated from the salient orifice mold, excellently enhanced the wafer-level uniformity of the orifice size and shape. We neatly demonstrated both the unified OPA of various orifice size and shape, and one corresponding to a 2400 dpi- inkjet printhead, using MESD method with a single-coated 41 micrometer-thick photoresist of Hoechst AZ9262.

Planarization and trench filling on severe surface topography with thick photoresist for MEMS

We have examined a simple and low-cost method to achieve planarization and trench filling on a severe surface topography for MEMS. The method simply uses a single-layer coating of a thick photoresist or polyimide, where the coating thickness is much greater than the severe surface topography. From extensive experiments, we extracted simple empirical formulae for the planarization factor (beta) of the thick photoresist AZ4562 and polyimide PI2611, which let us know the minimum film thickness required to obtain a certain (beta) on a given surface step height and pattern density. We could compare the planarization capability of AZ4562 and PI2611 by this method. Moreover, after the planarization with a thick photoresist, we have shown a new way, other than the plasma etching, to remove the upper photoresist layer conformally. Therefore, we could remain the photoresist only in trenches and fill up very deep and wide trenches with the photoresist. Also, we have shown the etch-back result of PI2611 using conventional O2 plasma RIE. Using these methods, we obtained the (beta) of 98% on the surface of 20 micrometer-deep and 200 micrometer-wide lines and spaces with a single-coated 70 micrometer-thick photoresist. And 10-micrometer-deep and 200 micrometer-wide trenches as well as 2 micrometer-deep and 50 micrometer-wide trenches were neatly filled up with the photoresist. As applications for MEMS, we fabricated microchannels by metal coating after the trench fill-up process, and even multilevel microchannels by controlling the height of the photoresist remaining in the trench and repeating the trench fill-up process.