Jae-Duk Lee

Effects of floating-gate interference on NAND flash memory cell operation

Introduced the concept of floating-gate interference in flash memory cells for the first time. The floating-gate interference causes V/sub T/ shift of a cell proportional to the V/sub T/ change of the adjacent cells. It results from capacitive coupling via parasitic capacitors around the floating gate. The coupling ratio defined in the previous works should be modified to include the floating-gate interference. In a 0.12-/spl mu/m design-rule NAND flash cell, the floating-gate interference corresponds to about 0.2 V shift in multilevel cell operation. Furthermore, the adjacent word-line voltages affect the programming speed via parasitic capacitors.

Effects of interface trap generation and annihilation on the data retention characteristics of flash memory cells

It is revealed that the interface trap generation rate increases by Fowler-Nordheim current stressing on the tunnel oxide as the channel width of shallow-trench isolation (STI)-isolated NAND flash cells shrinks. Furthermore, we argue that the interface trap annihilation phenomenon during retention mode becomes a major failure mechanism of the data retention characteristics of sub-100-nm cells in addition to the conventional charge loss mechanism. A new interface trap analysis method using the hysteresis of the I/sub d/--V/sub g/ curve is proposed and shows that the interface traps consist of fast traps and slow traps.

Degradation of tunnel oxide by FN current stress and its effects on data retention characteristics of 90 nm NAND flash memory cells

We have verified that as the cell transistor width decreases below 100 nm for the NAND flash memory interface trap generation increases rapidly by FN current stress on the tunnel oxide. Accordingly, in contrast to the SILC (Stress-Induced Leakage Current) mechanism for the large dimensional cell transistors, it is revealed that the major failure mechanism of the data retention of 90 nm cell transistors is the relaxation of interface traps, which consist of the fast and slow traps. For the interface trap analysis, a new analysis method using I/sub d/-V/sub g/ hysteresis curve is proposed.

A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system

A 64-Mbit bidirectional data strobed, double-data-rate SDRAM achieves a peak bandwidth of 2.56 GByte/s on a 64-bit-channel, 256-MByte memory system at V/sub cc/=3.3 V and T=25/spl deg/C. The circuit features are: (1) a bidirectional data strobing scheme to eliminate the clock-related skews of I/O data in a multimodule system, (2) a low-power delay-locked loop having a wide range of locking frequency (40-160 MHz) with fast access time and minimal variations, and (3) a twisted data bussing architecture with minimized loading difference between I/O data paths and small chip-size overhead associated with the 2-bit prefetch operation.

Insight Into N/PBTI Mechanisms in Sub-1-nm-EOT Devices

New insights into the negative/positive bias temperature instability (N/PBTI) degradation mechanisms in the sub-1-nm equivalent oxide thickness (EOT) regime are presented in this paper. The electric field requirements suggested by the International Roadmap for Semiconductors demand an even higher value in the sub-1-nm-EOT regime, which is practically difficult to meet with the increased hole trapping mechanism involved. Thus, a fixed electric field target of 5 MV/cm is considered as well here, which might be a reasonable target to achieve. The sub-1-nm-EOT devices in this paper are obtained by adopting a thinner TiN metal gate inducing Si in-diffusion and reducing the interfacial oxide layer thickness. NBTI degradation follows an isoelectric field model in over an EOT of 1 nm due to the degradation mechanism of Si/SiO_2 interface state generation combined with a hole trapping mechanism. However, in the sub-1-nm-EOT regime, the probability of hole trapping into the gate dielectric increases, and it is strongly dependent on the thickness of the interfacial oxide layer. Several experimental proofs of this increased bulk defect effect are shown in this paper. In addition, the bulk defect affecting NBTI is shown to be mostly a preexisting defect, although the permanently generated defects are relatively higher in sub-1-nm-EOT devices. Therefore, NBTI in the sub-1-nm-EOT regime faces the lifetime limit by both electric field dependence and increased degradation by increased hole trapping into bulk defects. Further, we found a minimum interfacial layer thickness of 0.4 nm that is required to prevent the accelerated NBTI degradation by increased direct tunneling. The main degradation mechanism of PBTI in sub-1-nm EOT is the electron trapping into bulk defects, which is the same as in over 1-nm-EOT devices. This enables us to modulate the bulk defect energetic locations in the oxide and to improve PBTI.

Data retention characteristics of sub-100 nm NAND flash memory cells

In contrast to the conventional theories, we have revealed that the most distinguished mechanism in the data retention phenomenon after Fowler-Nordheim (FN) stress in sub-100 nm NAND Flash memory cells is the annihilation of interface states. Interface state generation rate increases rapidly as the channel width of NAND flash cell decreases. Comparison of interface states and stress-induced leakage current (SILC) component during retention mode shows that the annihilation of interface states strongly affects data retention characteristics of the programmed cells.

High-performance 1-Gb-NAND flash memory with 0.12-/spl mu/m technology

A 1.8-V, 1-Gb NAND flash memory is fabricated with 0.12-/spl mu/m CMOS STI process technology. For higher integration, a 32-cell NAND structure, which enables row decoder layout in one block pitch, is applied for the first time. Resulting cell and die sizes are 0.076 /spl mu/m/sup 2/ and 129.6 mm/sup 2/, respectively. A pseudo-4-phase charge pump circuit can generate up to 20 V even under the supply voltage of 1.6 V. A newly applied cache program function and expanded page size of (2 k + 64) byte lead to program throughput of 7 MB/s. The page copy-back function is provided for on-chip garbage collection. The read throughput of 27 MB/s is achieved by simply expanding I/O width and page size. A measured disturbance free-window of 3.5 V at 1.5 V-V/sub DD/ is obtained.

Scaling and reliability of NAND flash devices

Numerous scaling limitations of NAND flash memory have arisen due to the intrinsic nature of the operational principle of NAND flash memory and those limitations eventually lead to a paradigm shift in the NAND flash technology from the planar cell to the vertical NAND cell. In this paper, the limitations of scaling which induce the evolution of the NAND cell as well as the current trends of NAND technology are reviewed.

A 2 Gb NAND flash memory with 0.044 /spl mu/m/sup 2/ cell size using 90 nm flash technology

A manufacturable 2 Gb NAND flash memory with 0.044 /spl mu/m/sup 2/ cell size, which is the smallest cell size ever reported in semiconductor memory, is successfully developed with 90 nm NAND flash technology for high density file storage application. The three main key technology features of 90 nm NAND flash technology are advanced KrF lithography with off-axis illumination system equipped with a dipole aperture, reduced stack height of cell, and optimized gate reoxidation affecting tunnel oxide profile.

A new floating gate cell structure with a silicon-nitride cap layer for sub-20 nm NAND flash memory

A new cell structure of NAND memory devices, which employs an additional nitride layer between the top of a floating gate (FG) and inter-poly dielectrics (IPD), is devised to lesson a high electric field on the FG top edges during program. The cell structure is proved to be promising in sub-20 nm NAND generation in terms of larger program window, better endurance, and more robust data retention, which are obtained by decreasing a leakage current of IPD relating with the electric field on the FG top edges.