Chul-Won Ju

Embedded passive components in MCM-D for RF applications

The increasing demand for high density packaging was the driving forces to the development of MCM-D technology. Most of these development efforts have been focused on high performance digital circuits. However, recently there is a great need for mixed mode circuits with a combination of digital, analog and microwave devices. Mixed mode modules often have a large number of passive components that are connected to a small number of active devices. Integration of passive components into the high density MCM substrate becomes desirable to further reduce cost, size, and weight of electronic systems while improving their performance and reliability. So, we developed the embedded passive components (including resistors, capacitors, inductors) for RF module in MCM-D substrate. This paper will describe the manufacturing process of MCM-D substrate, the method for integrating passive components in MCM-D substrate and electrical performance test.

Effects of O/sub 2//C/sub 2/F/sub 6/ plasma descum with RF cleaning on via formation in MCM-D substrate using photosensitive BCB

In this paper, we present the effect of plasma descum by O/sub 2//C/sub 2/F/sub 6/ gas mixture on the via formation of photosensitive BCB layer and compare it with that of RF cleaning. Test vehicle was fabricated on Si wafer with Cu/photosensitive BCB layer structure and ECR-CVD system was used to descum the via. Residues at via bottom after the descum process were investigated by AES (auger electron microscope) and SEM (scanning electron microscope). It is shown in this work that O/sub 2//C/sub 2/F/sub 6/ plasma etching and the RF cleaning are effective for organic C, native C respectively, therefore the via descum by a combination of plasma etching with O/sub 2//C/sub 2/F/sub 6/ gas mixture and RF cleaning can efficiently remove the via residues.

The effect of via size on fine pitch and high density solder bumps for wafer level packaging

This study investigated how the shapes of high density electroplated bump and reflowed bumps depend on via size. The solder bump was fabricated by subsequent processes as follows. After sputtering a Ti/Cu seed layer on a 5-inch Si-wafer, a thick photoresist for via formation was obtained by multi-coating, and vias with various diameters were defined by a conventional photolithography technique using a contact aligner with an I-line source. After via formation, eutectic solder bumps were electroplated. After reflow, the reflowed bump diameters at the bottom were unchanged compared with the electroplated diameters. The electroplated bump and reflowed bump shapes, however, depended significantly on the via size. The heights of the electroplated bumps and reflowed bumps increased with a larger via, while the aspect ratio of bumps decreased. To obtain high density bumps, the bump pitch was decreased so that the nearest bumps touched. The touching between the nearest bumps occurred during the over-plating procedure but not during the reflowing procedure because the mushroom diameter formed by over-plating was larger than the reflowed bump diameter. This study demonstrated that an arrangement in zig-zag rows is effective in realizing flip chip interconnect bumps with both a high density and high aspect ratio.

A high density multichip module for 2.48 Gb/s ATM switching system

We have developed a new MCM of 16/spl times/16 ATM switching elements handling a total signal throughput of 2.48 Gb/s by routing 16 trunk lines of 155 Mbps. This paper will describe the Cu/BCB multilayer process, basic electrical properties of MCM-D interconnect, MCM features in terms of specifications, structure, and assembly and module functional test.

Formation of Fine Pitch Solder Bump with High Uniformity by the Tilted Electrode Ring

The plating shape in the opening of photoresist becomes gradated shape in the fountain plating system, because bubbles from the wafer surface are difficult to escape from the deep openings, vias. In this paper, the bubble flow from the wafer surface during plating process was studied and we designed the tilted electrode ring to get uniform bump height on all over the wafer and evaluated the film uniformity by SEM and . In a-step measurement, film uniformities in the fountain plating system and the tilted electrode ring contact system were respectively.

A limiting amplifier module using wafer level package for 10Gbps optical transmission system

A 10 Gb/s limiting amplifier IC with the emitter area of 1.5xlOpn1~ for optical transmission system was designed and fabricated with a AIGaAs/GaAs HBTs technology. In this study. we evaluated fme pitch bump using WL-CSP (Wafer This paper describes the design and fabrication of lOGbps limiting amplifier using AIGaAdGaAs HBTs for the optical transmission system and the development of fme pitch WLCSP process. Finally the frequency response and eye diagram of the limiting amplifier package module are discussed. Level-Chip Scale Packag-ing) instead of conventional wire bonding for interconnection. To study the effect of WL-CSP, electrical performance was measured and analyzed in wafer and package module using WL-CSP. In a package module, clear and wide eye diagram openings were observed and the rise/fall times were about 9@s, and the output voltage swing was limited to 65OmV,, with input voltage ranging from 50 to 50OmV. The Small signal gains in wafer and package module were 16.25dB and 14.86dB respectively. It was found that the difference of small signal gain in wafer and package module was less then 1.5dB up to 1OGHz. But, the characteristics of return loss was improved in package module. This is due to the short interconnection length by WL-CSP. In this study, we developed fine pitch bump with the 40pm diameter and 100 p m pitch using WL-CSP process. So, WLCSP process can be used for millimeter wave GaAs MMIC with the fme pitch pad.