Hee-Tae Lee

Laser weldability analysis of high-speed optical transmission device packaging

A 2.5 Gb/s distributed feedback laser diode (DFB-LD) module was used as a test package to develop laser welding techniques. Various package weld joint geometries, such as lap, fillet, butt, and fillet-lap, were designed and welded to investigate the optimal package configuration that leads to the maximum coupling efficiency and minimum weld shift. Furthermore, the welded joints at a given set of laser parameters were cross-sectioned for metallurgical analysis, such as weld penetration and microcracks, for verification of the weld joint integrity. Through such analysis, some important laser welding parameters, such as depth-of-penetration (DOP), heat-affected zone (HAZ), shear-strength, and solidification formation of the weld pool were analyzed. Also, as the result of investigating 56 laser welded DFB-LD submodules, optimal laser parameters, and the suitable joint geometry for this package could be determined with the average weld shift less than 0.19 dB, which translates to less than 1.0 /spl mu/m in radial displacement. These laser welded packages exhibited an excellent tracking stability during environmental testing, which consequently resulted in obtaining a desirable bit-error rate (BER) during the data transmission performance analysis.

Fabrication of semiconductor optical switch module using laser welding technique

The 4/spl times/4, 1/spl times/2, and 1/spl times/4 semiconductor optic-switch modules for 1550 nm optical communication systems were fabricated by using the laser welding technique based on the 30-pin butterfly package. For better coupling efficiency between a switch chip and an optical fiber, tapered fibers of 10-15 /spl mu/m lens radius were used to provide the coupling efficiency up to 60%. The lens to lens distance of the assembled tapered fiber array was controlled within /spl plusmn/1.0 /spl mu/m. A laser hammering technique was introduced to adjust the radial shift, which was critical to obtain comparable optical coupling efficiencies from all the channels at the same time. The fabricated optical switch modules showed good thermal stability, with less than 5% degradation after a 200 thermal cycling. The transmission characteristics of the 4/spl times/4 switch module showed good sensitivities, providing error free transmissions below -30 dBm for all the switching paths. The dynamic ranges for the 4/spl times/4 and 1/spl times/2 switch modules were about 8 dB for a 3 dB penalty and about 17 dB for a 2 dB penalty, respectively.

High frequency modeling for 10 Gbps DFB laser diode module packaging

In packaging the laser diode several electrical requirements must be satisfied. The conventional packaging method which consists of transmission line, matching resistor and wire bonding interconnect showed good result for the modulation bandwidth requirement of greater than 10 GHz. However the return loss requirement was not content with less than -10 dB. To analyze the effects of package parasitics on return loss, we proposed a small signal circuit model of a laser diode module. From the small signal measurement data, we obtained the small signal circuit model of the laser diode for each bias current, which contains package parasitics and intrinsic laser diode characteristics. Considering both the intrinsic laser diode characteristics and total parasitic effects of the packaged module, the overall frequency response of the laser diode module was simulated and compared to the experimental results. The simulation results on the small signal modulation bandwidth and return loss showed a good agreement with measurements. However, the return loss does not meet the requirement for 10 Gbps laser diode module. Therefore, the wire bonding effect on the return loss was analyzed. The characteristics of wire bonding inductance which affect the return loss were simulated using an interconnect analysis program. As a result, shorter wire bonding length would be the best step to reduce the package induced inductance.

Effects of O/sub 2//C/sub 2/F/sub 6/ plasma descum with RF cleaning on via formation in MCM-D substrate using photosensitive BCB

In this paper, we present the effect of plasma descum by O/sub 2//C/sub 2/F/sub 6/ gas mixture on the via formation of photosensitive BCB layer and compare it with that of RF cleaning. Test vehicle was fabricated on Si wafer with Cu/photosensitive BCB layer structure and ECR-CVD system was used to descum the via. Residues at via bottom after the descum process were investigated by AES (auger electron microscope) and SEM (scanning electron microscope). It is shown in this work that O/sub 2//C/sub 2/F/sub 6/ plasma etching and the RF cleaning are effective for organic C, native C respectively, therefore the via descum by a combination of plasma etching with O/sub 2//C/sub 2/F/sub 6/ gas mixture and RF cleaning can efficiently remove the via residues.

Reliability considerations of laser diodes for optical communication system application

The purpose of this paper is to propose a reliability parameter of laser diodes for optical communication system applications. Based on the alarm function in optical communication systems, we have developed a reliability parameter; /spl rho//sub a/(=/spl eta//sub a///spl eta//sub 0/.Ith/sub a//Ith/sub 0/)/spl ges/1.5, which is more applicable to estimate reliability projections and to design LD modules for optical communication systems.

The effect of via size on fine pitch and high density solder bumps for wafer level packaging

This study investigated how the shapes of high density electroplated bump and reflowed bumps depend on via size. The solder bump was fabricated by subsequent processes as follows. After sputtering a Ti/Cu seed layer on a 5-inch Si-wafer, a thick photoresist for via formation was obtained by multi-coating, and vias with various diameters were defined by a conventional photolithography technique using a contact aligner with an I-line source. After via formation, eutectic solder bumps were electroplated. After reflow, the reflowed bump diameters at the bottom were unchanged compared with the electroplated diameters. The electroplated bump and reflowed bump shapes, however, depended significantly on the via size. The heights of the electroplated bumps and reflowed bumps increased with a larger via, while the aspect ratio of bumps decreased. To obtain high density bumps, the bump pitch was decreased so that the nearest bumps touched. The touching between the nearest bumps occurred during the over-plating procedure but not during the reflowing procedure because the mushroom diameter formed by over-plating was larger than the reflowed bump diameter. This study demonstrated that an arrangement in zig-zag rows is effective in realizing flip chip interconnect bumps with both a high density and high aspect ratio.

An empirical lifetime projection method for laser diode degradation

An empirical method for lifetime projection of 1.55 /spl mu/m InGaAs-InP MQW-DFB laser diodes (LD) is presented. On the basis of experimental results of an accelerated aging test for 1500 hours, relationship between LD degradation, operating voltage, and ambient temperature has been determined. The presented method makes it possible to predict the lifetime of LDs by determining the thermal voltage ratio.

An empirical reliability prediction method for 1.55 /spl mu/m InGaAs/InP MQW-DFB laser diodes

An empirical method for lifetime projection of 1.55 /spl mu/m InGaAs/InP MQW-DFB laser diodes (LD) is presented. On the basis of experimental results of accelerated aging test for 1500 hours, relationship between LD degradation, operating voltage, and ambient temperature has been determined. The presented method makes it possible to predict the lifetime of LDs by determining the thermal voltage ratio.

Pb/In solder bump formation for a flip-chip bonding technique at high speed optical communication devices

The increasing speed of advanced chip technologies has greatly challenged the interconnection methods and processes in order to achieve enhanced capability. We have successfully fabricated the solder bump and its reflowing process for flip-chip bonding interconnection technique instead of conventional wire bonding for high speed devices. The lead (Pb: 350/spl deg/C) and the Indium (In: 157/spl deg/C) were used for solder bump and deposited by using thermal evaporation. The thickness of the deposited metal for solder bump was in the range of 5/spl sim/6 /spl mu/m thickness. Specially, to increase the accuracy and the reliability of the flip-chip bonding Technique, 3 layer thick photoresist about 30 /spl mu/m was used to control the deposition area for solder bump. It was also used for the lift-off process of excess deposited metal for solder bump. The height of solder bump through the reflowing process was controlled in the range of 10/spl sim/40 /spl mu/m according to the deposited area and shape. Also, the deposited area and shape was one of the most important parameters for solder bump fabrication. In addition, it was found that an oxidized surface layer effects on the increased melting temperature of deposited metal for solder bump. In this process, the reflowing temperature of PB/In (60:40 wt%) solder bumps was 230/spl plusmn/5/spl deg/C.

Reliability purge test of SAGCM InGaAs/InP APDs

The purpose of this paper is to propose a high reliability purge condition for separate absorption, grading, charge, and multiplication (SAGCM) InGaAs/InP avalanche photodiodes (APDs) for fiber optical transmission systems. We have found that infant failures of the InGaAs/InP APDs can be purged out by applying 90% of the reverse breakdown voltage at an ambient temperature of 100/spl deg/C for a minimum of 6 hours. The physical mechanism of the infant failures is a positive interfacial trapped charge causing decrease in breakdown voltage and an increase in dark current.