Chulwoo Kim

Low Power Flip-Flop and Clock Network Design Methodologies in High-Performance System-on-a-Chip

In many VLSI (very large scale integration) chips, the power dissipation of the clocking system that includes clock distribution network and flip-flops is often the largest portion of total chip power consumption. In the near future, this portion is likely to dominate total chip power consumption due to higher clock frequency and deeper pipeline design trend. Thus it is important to reduce power consumptions in both the clock tree and flip-flops. Traditionally, two approaches have been used: 1) to reduce power consumption in the clock tree, several low-swing clock flip-flops and double-edge flip-flops have been introduced; 2) to reduce power consumption in flip-flops, conditional capture, clock-on-demand, data-transition look-ahead techniques have been developed. In this chapter these flip-flops are described with their pros and cons. Then, a circuit technique that integrates these two approaches is described along with simulation results. Finally, clock gating and logic embedding techniques are explained as powerful power saving techniques, followed by a low-power clock buffer design.