Dongsuk Shin

Effects of Morphological Changes of Pt/SrBi2Ta2O9 Interface on the Electrical Properties of Ferroelectric Capacitor

Morphological changes have been observed at the interface of Pt/SrBi2Ta2O9 (SBT) before and after annealing at 600 and 800°C after depositing Pt top electrode. We have investigated leakage currents, breakdown voltages, and capacitances of Pt/SBT/Pt /SiO2/Si capacitor and Pt/SBT/CeO2/Si gate structure. As a result, the leakage current density and capacitance are reduced from 10-7 to 10-8 A/cm2 and 1.3×10-10 to 8.5×10-11 F/cm2, respectively, and breakdown voltage increases from 5 to 14 V after post-annealing. The reduced leakage current density and increased breakdown voltage in the annealed samples are due to the smooth morphology of the interface of Pt/SBT. In the as-deposited Pt top electrode on SBT films, high electric field intensity is generated due to small arc of the valleys filled with fine Pt grains, resulting in higher leakage current density than the post-annealed Pt top electrode. Although the total gate capacitance of the post-annealed sample is reduced by the non-contact area due to voids at the interface of Pt/SBT, memory window of the ferroelectric gate is not influenced by such voids.

Electrical Properties of Pt/SrBi2Ta2O9/CeO2/SiO2/Si Structure for Nondestructive Readout Memory

Memory window and leakage current density of Pt/SrBi2Ta2O9/CeO2/SiO2/Si structure have been investigated for non destructive read out memory. Coercive field that decisively affects on the memory window becomes greater by the interposition of the CeO2 insulator between SrBi2Ta2O9 and SiO2 and thus the memory window also increases with an electric field to the SrBi2Ta2O9. A typical value of memory window for Pt/SrBi2Ta2O9(140 nm)/CeO2/SiO2/Si is in the range of 0.5 – 3.0 V, which is high enough for the non destructive read out memory, at the applied voltage of 3 – 9 V. The leakage current density is remained at 3 ×10-8 A/cm2 until the applied voltage increases up to 10 V.

Effects of Bi-Pt alloy on electrical characteristics of Pt/SrBi2Ta2O9/CeO2/Si ferroelectric gate structure

Interface morphology and electrical properties of Pt/SrBi2Ta2O9(SBT)/CeO2/Si ferroelectric gate structure are characterized by considering the interactions among Bi, O, and Pt atoms during annealing process. It is found that the interfacial roughness of the Pt/SBT might be reduced during the annealing at 800u200a°C because the bottom side of the Pt electrode reacts with Bi atoms outdiffused from the SBT and the Bi–Pt alloys are molten at 765u200a°C, and the metallic Bi atoms are consumed by forming Bi oxide. Additionally, the capacitance and memory window of the ferroelectric gate structure annealed at 800u200a°C decrease to 69% and 80% of those values of the as-deposited gate structure, respectively, due to the additional capacitance and the voltage drop at the low dielectric Bi-oxide capacitor. In contrast, the leakage current characteristics are improved by two orders of magnitude after annealing at 800u200a°C for 30 min.

A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time

A portable multiphase clock generator, independent of input duty ratio, has been developed. The proposed open-loop and full-digital architecture has a fast lock time of two clock cycles and is a simple, robust and portable IP. In addition, the complementary delay line is implemented to achieve high phase resolution at a wide frequency range. The generator has been implemented in a 0.18 um CMOS process and operates at variable input frequencies ranging from 800 MHz to 1.6 GHz.

A 7ps-Jitter 0.053mm2 Fast-Lock ADDLL with Wide-Range and High-Resolution All-Digital DCC

An ADDLL is designed to achieve low jitter, fast lock time and nearly 50% duty cycle with an open-loop duty-cycle corrector. The ADDLL operates over a frequency range from 440MHz to 1.5GHz with 15 cycles of maximum lock-in time and occupies 0.053mm2 in 0.18mum 1.8V CMOS. The peak-to-peak jitter is 7ps at 1.5GHz and the power consumption is 43mW.

SrBi2Ta2O9 thin films grown by MOCVD using a novel double metal alkoxide precursor

We have investigated the growth of Bi oxide, Sr–Ta oxide, and SrBi2Ta2O9 (SBT) thin films on Pt/SiO2/Si substrates by the MOCVD technique using a novel double metal alkoxide precursor, strontium and tantalum ethoxide (Sr[Ta(OEt)6]2), and triphenylbismuth [Bi(C6H5)3]. SBT films having ternary compositions were grown over a 500–700°C temperature range with polycrystalline films being attained after annealing at 800°C in oxygen. β-Bi2O3 phase was obtained after annealing as-grown films at 800°C in oxygen. Sr–Ta oxide films grown at 500°C substrate temperature had SrTa2O6 phase, which may be appropriate for growing SBT films having perovskite layer (SrTa2O7). Details of obtaining the necessary flow ratios of the two precursors are given along with SEM micrographs of the polycrystalline SBT film.

Wide frequency range duty cycle correction circuit for DDR interface

The proposed wide-range digital duty cycle correction (DCC) circuit corrects an arbitrary input clock duty ratio to 50% while preserving the output clock phase even when the input clock duty ratio suddenly changes. Also, DCC control information is preserved during power-down mode. In this work, for input frequency range of 500MHz to 2GHz with ±10% duty ratio error, the output duty ratio error is corrected to be less than ±1.4%. The proposed DCC circuit is designed and verified using a 0.18um CMOS technology.

A Low-Jitter Open-Loop All-Digital Clock Generator with 2 Cycle Lock-Time

A portable clock generator, which solves the duty ratio and jitter problems of the input clock, has been developed. In the proposed clock generator, the complementary delay line generates a series of multiphase clocks. The 0-to-1 transition detector finds the 2 pi phase delayed position among the multiphase clocks produced by the complementary delay line, and then, the select signal generator chooses the proper path to generate the delayed output clock. As a result, the proposed open-loop and full-digital architecture achieves a fast lock time of two clock cycles. Also, it is a simple, robust and portable IP and consumes only 17 mW at an input clock frequency of 1.6 GHz. In addition, a complementary delay line is implemented to achieve high phase resolution over a wide frequency range. The proposed clock generator is implemented in a 0.18-mum CMOS process and, occupies an active area of 170 mum times 120 mum. Also, it operates at various input frequencies ranging from 800 MHz to 1.6 GHz.

A 4-bit 2GSamples/s parallel Flash ADC using comb-type reference ladder

This paper describes a 4bit parallel flash Analog-to-Digital converter (ADC) using two sub Flash ADCs and comb-type reference ladder. High speed full flash ADCs have been suffered from input referred noise which is noise itself of analog input or noise inferred from reference ladder. As power supply voltage goes lower and resolution goes higher, noise inferred from reference ladder becomes more critical to ADCs performance. The proposed ADC consists of two parallel sub-ADCs with divided reference ladder to overcome degradation due to small reference voltage step. Simulation results show that the proposed ADC achieves 3.96 effective number of bit (ENOB) for 46MHz input signal and 3.94 ENOB for 1046MHz input signal at 2GHz sampling rate. At 2GSample/s, the current consumption is 45mA including digital logic with 1.8v power supply voltage. The proposed 4bit ADC is designed with 0.18um CMOS technology.

A New Energy × Delay-Aware Flip-Flop

This paper describes the Differential Pass Transistor Pulsed Latch (DPTPL) which enhances D-Q delay and reduce power consumption using NMOS pass transistors and feedback PMOS transistors. The proposed flip-flop uses the characteristic of stronger drivability of NMOS transistor than that of transmission gate if the sum of total transistor width is the same. Positive feedback PMOS transistors enhance the speed of the latch as well as guarantee the full-swing of internal nodes. Also, the power consumption of proposed pulsed latch is reduced significantly due to the reduced clock load and smaller total transistor width compared to conventional differential flip-flops. DPTPL reduces E × D by 45.5% over ep-SFF. The simulations were performed in a 0.1 μm CMOS technology at 1.2 V supply voltage with 1.25 GHz clock frequency.