Chun-Cheng Wang

A CMOS 210-GHz Fundamental Transceiver With OOK Modulation

This paper presents a 210-GHz transceiver with OOK modulation in a 32-nm SOI CMOS process (fT/fmax= 250/320 GHz). The transmitter (TX) employs a 2 × 2 spatial combining array consisting of a double-stacked cross-coupled voltage controlled oscillator (VCO) at 210 GHz with an on-off-keying (OOK) modulator, a power amplifier (PA) driver, a novel balun-based differential power distribution network, four PAs, and an on-chip 2 × 2 dipole antenna array. The noncoherent receiver (RX) utilizes a direct detection architecture consisting of an on-chip antenna, a low-noise amplifier (LNA), and a power detector. The VCO generates measured -13.5-dBm output power, and the PA shows a measured 15-dB gain and 4.6-dBm Psat. The LNA exhibits a measured in-band gain of 18 dB and minimum in-band noise figure (NF) of 11 dB. The TX achieves an EIRP of 5.13 dBm at 10 dB back-off from saturated power. It achieves an estimated EIRP of 15.2 dBm when the PAs are fully driven. This is the first demonstration of a fundamental frequency CMOS transceiver at the 200-GHz frequency range.

A W-band CMOS Receiver Chipset for Millimeter-Wave Radiometer Systems

This paper presents a W-band receiver chipset for passive millimeter-wave imaging in a 65 nm standard CMOS technology. The system comprises a direct-conversion receiver front-end with injection-locked tripler and a companion analog back-end for Dicke radiometer. The receiver design addresses the high 1/f noise issue in the advanced CMOS technology. An LO generation scheme using a frequency tripler is proposed to lower the PLL frequency, making it suitable for use in multi-pixel systems. In addition, the noise performance of the receiver is further improved by optimum biasing of transistors of the detector in moderate inversion region to achieve the highest responsivity and lowest NEP. The front-end chipset exhibits a measured peak gain of 35 dB, -3 dB BW of 12 GHz, NF of 8.9 dB, while consuming 94 mW. The baseband chipset has a measured peak responsivity (Rv) of 6 KV/W and a noise equivalent power (NEP) of 8.54 pW/Hz1/2. The two chipsets integrated on-board achieve a total responsivity of 16 MV/W and a calculated Dicke NETD of 1K with a 30 ms integration time.

A BiCMOS W-Band 2×2 Focal-Plane Array With On-Chip Antenna

This paper presents a W-band 2 × 2 focal-plane array (FPA) for passive millimeter-wave imaging in a standard 0.18 μm SiGe BiCMOS process (fT/fmax = 200/180 GHz). The FPA incorporates four Dicke-type receivers representing four imaging pixels. Each receiver employs the direct-conversion architecture consisting of an on-chip slot folded dipole antenna, an SPDT switch, a low noise amplifier, a single-balanced mixer, an injection-locked frequency tripler (ILFT), an IF variable gain amplifier, a power detector, an active bandpass filter and a synchronous demodulator. The LO signal is generated by a shared Ka-band PLL and distributed symmetrically to four local ILFTs. The measured LO phase noise is -93 dBc/Hz at 1 MHz offset from the 96 GHz carrier. This imaging receiver (without antenna) achieves a measured average responsivity and noise equivalent power of 285 MV/W and 8.1 fW/Hz1/2, respectively, across the 86-106 GHz bandwidth, which results a calculated NETD of 0.48 K with a 30 ms integration time. The system NETD increases to 3 K with on-chip antenna due to its low efficiency at W-band. MMW images have been generated in transmission mode. This work demonstrates the highest integration level of any silicon-based systems in the 94 GHz imaging band.

W-Band Silicon-Based Frequency Synthesizers Using Injection-Locked and Harmonic Triplers

Two monolithically integrated W-band frequency synthesizers are presented. Implemented in a 0.18 μm SiGe BiCMOS with fT/fmax of 200/180 GHz, both circuits incorporate the same 30.3-33.8 GHz PLL core. One synthesizer uses an injection-locked frequency tripler (ILFT) with locking range of 92.8-98.1 GHz and the other employs a harmonic-based frequency tripler (HBFT) with 3-dB bandwidth of 10.5 GHz from 90.9-101.4 GHz, respectively. The measured RMS phase noise for ILFT- and HBFT-based synthesizers are 5.4° and 5.5° (100 kHz to 100 MHz integration), while phase noise at 1 MHz offset is -93 and -92 dBc/Hz, respectively, at 96 GHz from a reference frequency of 125 MHz. The measured reference spurs are <; -52 dBc for both prototypes. The combined power consumption from 1.8- and 2.5-V is 140 mW for both chips. The frequency synthesizer is suitable for integration in millimeter-wave (mm-wave) phased array and multi-pixel systems such as W-band radar/imaging and 120 GHz wireless communication.

A 2-Gb/s 130-nm CMOS RF-Correlation-Based IR-UWB Transceiver Front-End

This paper presents a carrierless RF-correlation-based impulse radio ultra-wideband transceiver (TRX) front-end in a 130-nm CMOS process. Timing synchronization and coherent demodulation are implemented directly in the RF domain, targeting applications such as short-range energy-efficient wireless communication at gigabit/second data rates. The 6-10-GHz band is exploited to achieve higher data rate. Binary phase-shift keying modulated impulse is generated by edge combining the delayed clock signal at a lower frequency of 2 GHz to avoid a more power-hungry phase-locked loop at higher frequency (e.g., 8 GHz). An on-chip pulse shaper inside the pulse generator is designed to provide filtering for an edge-combined signal to comply with the Federal Communications Commission spectrum emission mask. In order to achieve 25-ps delay accuracy and 500-ps delay range for the proposed two-step RF synchronization, a template-based digital delay generation scheme is proposed, which delays the locally generated trigger pulse instead of the wideband pulse itself. Occupying 6.4 mm2 of chip area, the TRX achieves a maximum data rate of 2 Gb/s and a receiver (RX) sensitivity of -64 dBm with a bit error rate of 10-5, while requiring only 51.5 pJ/pulse in the transmitter mode and 72.9 pJ/pulse in the RX mode.

A 210GHz fully integrated differential transceiver with fundamental-frequency VCO in 32nm SOI CMOS

The vastly under-utilized spectrum in the sub-THz frequency range enables disruptive applications including 10Gb/s chip-to-chip wireless communications and imaging/spectroscopy. Owing to aggressive scaling in feature size and device fT/fmax, nanoscale CMOS technology potentially enables integration of sophisticated systems at this frequency range. For example, CMOS sub-THz signal sources and TRXs have been reported [1-4], employing techniques such as distributed active radiator (DAR) and super-harmonic signal generator. The lack of RF amplification in CMOS sub-THz TRXs reported in prior work, however, results in low efficiency (and thus higher power dissipation), and high noise-figure (NF). This paper addresses these issues by demonstrating a 210GHz TRX with on-off-keying (OOK) modulation incorporating a 2×2 TX antenna array, a 2×2 spatial combining power amplifier (PA), a fundamental frequency VCO, and a low noise amplifier (LNA) in a 32nm SOI CMOS process (fT/fmax=250/350GHz).

A 2Gbps RF-correlation-based impulse-radio UWB transceiver front-end in 130nm CMOS

The design of a carrier-less RF-correlation-based IR-UWB TRX front-end in 130nm CMOS is presented. Timing synchronization and coherent demodulation are implemented directly in the RF domain, enabling energy-efficient wireless communication at Gb/s data rates. A 25ps timing resolution is achieved by a two-step synchronizer. Occupying 6.4mm2 chip area, the TRX achieves a maximum data rate of 2Gbps and an RX sensitivity of −64dBm with a BER of 10−5, while requiring only 51.5pJ/pulse in the TX mode and 72.9pJ/pulse in the RX mode.

A fully integrated 96GHz 2×2 focal-plane array with On-Chip antenna

A fully integrated 96GHz 2×2 focal-plane array (FPA) direct conversion imager in 0.18µm SiGe BiCMOS (f<inf>T</inf>/ƒ<inf>max</inf>=200/180GHz) employing four integrated antennas with Dicke switches and LO generation/distribution is presented. The PLL plus tripler achieves a locking range of 92.67–98.2GHz and phase noise of −93dBc/Hz at 96GHz measured at 1MHz offset. The 3.5×3mm² chip achieves an average responsivity and NEP of 285MV/W and 8.1fW/√Hz, respectively, across 86–106GHz band and an NETD of 0.48K. The chip consumes 695mW from 1.8V/2.5V supplies.

A 80-92-GHz Receiver Front-End Using Slow-Wave Transmission Lines in 65nm CMOS

Slow-wave coplanar waveguides (SW-CPW) are promising candidates for realization of low-loss and compact on-chip passive components at millimeter-wave (MMW) frequencies. To meet the stringent pattern density requirement of nanoscale CMOS, two types of dummy prefills are proposed. The transmission lines achieve a measured effective dielectric permittivity of 20 and 10, an attenuation of 1 and 0.5 dB/mm, a quality factor of 15 and 20 and a figure-of-merit of 0.2 dB/rad, all at 40 GHz. A W-band front-end receiver based entirely on the characterized SW-CPW with frequency tripler as the LO is measured. The receiver achieves a total gain of 35-dB, a NF of 9-dB, a P-1dB of -40-dBm, a low power consumption of 108mW under 1.2/0.8V and a FOM of 0.49.