Fred Tzeng

A single-chip dual-band 22-to-29GHz/77-to-81GHz BiCMOS transceiver for automotive radars

In the last few years, silicon-based 24GHz short-range automotive radars have been investigated both by industry and academia [1,2]. Intensive research/development is also underway for developing 77GHz long-range [3] and 77-to-81GHz short-range radars [4] in silicon technologies. While ETSI will discontinue the use of the 24GHz allocation for automotive short-range sensors in mid-2013 [5], thereafter mandating a shift to 79GHz, mature 24GHz technology will continue to dominate non-European markets. Therefore, next-generation radar sensors may well be required to support both frequency bands, for compatibility and lower overall cost. This paper presents a dual-band millimeter-wave (mmWave) transceiver (TRX) in a 0.18µm BiCMOS technology (fT/fmax=200/180GHz). The dual-band TRX operates in the 22-to-29GHz and 77-to-81GHz short-range automotive radar bands.

A Multiband Inductor-Reuse CMOS Low-Noise Amplifier

This paper presents the design and implementation of a new multiband, multistandard CMOS low-noise amplifier (LNA) that reuses inductors for different frequency bands to minimize chip area. The idea is to adaptively reconfigure a CMOS transistor in either common source or common gate configuration to achieve narrow-band (NB) or wide-band (WB) input matching, respectively, while conveniently reusing input and load inductors for both bands. This architecture is suitable for 802.11 a/b/g and Public Safety Broadband (PSB) applications, where the NB configuration covers wireless local area network (WLAN) 802.11 b/g, while the WB configuration accommodates the PSB at 4.9 GHz and WLAN 802.11 a. Two versions of the proposed idea, a tapped-capacitor and a tapped-inductor input-matched LNA, have each been designed and fabricated in 0.13-mum CMOS and measurement results are demonstrated.

A 2-Gb/s 130-nm CMOS RF-Correlation-Based IR-UWB Transceiver Front-End

This paper presents a carrierless RF-correlation-based impulse radio ultra-wideband transceiver (TRX) front-end in a 130-nm CMOS process. Timing synchronization and coherent demodulation are implemented directly in the RF domain, targeting applications such as short-range energy-efficient wireless communication at gigabit/second data rates. The 6-10-GHz band is exploited to achieve higher data rate. Binary phase-shift keying modulated impulse is generated by edge combining the delayed clock signal at a lower frequency of 2 GHz to avoid a more power-hungry phase-locked loop at higher frequency (e.g., 8 GHz). An on-chip pulse shaper inside the pulse generator is designed to provide filtering for an edge-combined signal to comply with the Federal Communications Commission spectrum emission mask. In order to achieve 25-ps delay accuracy and 500-ps delay range for the proposed two-step RF synchronization, a template-based digital delay generation scheme is proposed, which delays the locally generated trigger pulse instead of the wideband pulse itself. Occupying 6.4 mm2 of chip area, the TRX achieves a maximum data rate of 2 Gb/s and a receiver (RX) sensitivity of -64 dBm with a bit error rate of 10-5, while requiring only 51.5 pJ/pulse in the transmitter mode and 72.9 pJ/pulse in the RX mode.

Code-modulated path-sharing multi-antenna receivers: theory and analysis

Conventional multi-antenna receiver front-ends require multiple RF/baseband chains and analog-to-digital converters (ADC). This increases power consumption and chip area substantially. In this letter, we introduce a new Code-Modulated Path-Sharing Multi-Antenna (CPMA) receiver architecture suitable for any multi-antenna scheme including spatial multiplexing, spatial diversity, and beamforming. The receiver uses code modulation to distinguish the antenna signals before combining them in the analog domain. The combined signal propagates through shared-path blocks and all the original signals are later recovered in the digital domain for further processing. Due to the spread spectrum nature of code modulation, a larger bandwidth is needed for the blocks in the shared path. To alleviate this effect, the use of non-orthogonal coding is examined. An effective channel matrix is derived and the system capacity is evaluated in terms of the cross-correlation between signature codes. Implementation and code selection issues are discussed. Analysis and simulation results indicate that by properly selecting non-orthogonal code sets, the spreading factor, and therefore, the overall analog signal bandwidth is reduced while incurring minimal performance degradation.

Theoretical Analysis of Novel Multi-Order LC Oscillators

A conventional differential pair LC oscillator is capable of generating only a single fundamental oscillation frequency. This brief presents the theoretical study of a novel oscillator that incorporates higher order LC filters to produce multiple oscillation frequencies that may be several octaves apart. These multiple oscillation frequencies are obtained from a single oscillator, thereby reducing the area of the circuit when being used for multistandard wireless applications. Moreover, a multi-order oscillator does not suffer from large parasitic capacitances from switches, which is a common drawback in switched-inductor tuned oscillators. A detailed analysis is carried out, and useful design insights are provided

A CMOS Code-Modulated Path-Sharing Multi-Antenna Receiver Front-End

This paper presents the design and implementation of a novel multi-antenna receiver front-end, which is capable of accommodating various multi-antenna schemes including spatial multiplexing (SM), spatial diversity (SD), and beamforming (BF). The use of orthogonal code-modulation at the RF stage of multi-antenna signal paths enables linear combination of all mutually orthogonal code-modulated RF received signals. The combined signal is then fed to a single RF/baseband/ADC chain. In the digital domain, all antenna signals are fully recovered using matched filters. Primary advantages of this architecture include a significant reduction in area and power consumption. Moreover, the path-sharing of multiple RF signals mitigates the issues of LO routing/distribution and cross-talk between receive chains. System-level analyses of variable gain/dynamic range, bandwidth/area/power trade-off, and interferers are presented. Designed for the 5-GHz frequency and fabricated in 0.18 mum CMOS, the 76 mW 2.3 mm2 two-antenna receiver front-end prototype achieves a 10-2 symbol error rate (SER) at 64, 77, and 78 dBm of input power for SM, SD, and BF, respectively, while providing 21-85 dB gain, 6.2 dB NF, and 10.6 dBm IIP3.

Polar Quantizer for Wireless Receivers: Theory, Analysis, and CMOS Implementation

This paper presents the theory and analysis of IF polar receiver (PRX) architecture. By using new quantization techniques in the polar domain, the proposed receiver can boost the signal to quantization noise ratio (SQNR) compared to a traditional rectangular (I/Q) receiver. The proposed PRX is composed of a magnitude and a phase quantizer. The magnitude quantizer is similar to the conventional rectangular quantizer in voltage domain. The phase quantizer employs a time-to-digital converter (TDC) for phase detection. Furthermore, an intuitive graphical method is used to analyze the quantization properties of the polar quantization. A 10 bit polar quantizer is designed and fabricated in 130 nm CMOS, and achieves 2- to 5-dB of SQNR improvement compared to rectangular quantizer for signal bandwidths as high as 20 MHz.

A 2Gbps RF-correlation-based impulse-radio UWB transceiver front-end in 130nm CMOS

The design of a carrier-less RF-correlation-based IR-UWB TRX front-end in 130nm CMOS is presented. Timing synchronization and coherent demodulation are implemented directly in the RF domain, enabling energy-efficient wireless communication at Gb/s data rates. A 25ps timing resolution is achieved by a two-step synchronizer. Occupying 6.4mm2 chip area, the TRX achieves a maximum data rate of 2Gbps and an RX sensitivity of −64dBm with a BER of 10−5, while requiring only 51.5pJ/pulse in the TX mode and 72.9pJ/pulse in the RX mode.

Design and analysis of a current-reuse transmitter for ultra-low power applications

A CMOS current-reuse transmitter for ultra-low power (ULP) applications is presented. It can provide up to 10.2dBm of output power with a total efficiency of 30% at 2.4GHz. By utilizing the stacking technique, the average current of a class-E power amplifier is reused by the accompanying VCO and an optional RX block. The breakdown issue associated with the class-E PA is mitigated. A detailed analysis of the current-reuse structure is demonstrated. Practical design issues are discussed and appropriate design guidelines are provided.

A Universal Code-Modulated Path-Sharing Multi-Antenna Receiver

Conventional multi-antenna systems require multiple RF chains, baseband blocks, and analog-to-digital converters (ADC) in the receiver front-end, mandating substantial increases in power consumption and chip area. In this paper, we introduce a new universal code-modulated path-sharing multi-antenna (CPMA) receiver architecture suitable for any multi-antenna scheme including spatial multiplexing and spatial diversity. The receiver utilizes code modulation to distinguish different antenna signals before combining them in the analog domain. The combined signals propagate through a single shared path and are later recovered in the digital domain for further processing. Due to the spread spectrum nature of code modulation, a larger bandwidth is required for the blocks in the shared path. To alleviate this effect, we examine the use of non-orthogonal signature codes. Analysis and simulation results indicate that by properly selecting non-orthogonal code sets, the spreading factor, and therefore, the overall analog signal bandwidth is reduced while incurring minimal performance degradation.