Chun Chi Yu

Device-correlated metrology for overlay measurements

Abstract. One of the main issues with accuracy is the bias between the overlay (OVL) target and actual device OVL. In this study, we introduce the concept of device-correlated metrology (DCM), which is a systematic approach to quantify and overcome the bias between target-based OVL results and device OVL values. In order to systematically quantify the bias components between target and device, we introduce a new hybrid target integrating an optical OVL target with a device mimicking critical dimension scanning electron microscope (CD-SEM) target. The hybrid OVL target is designed to accurately represent the process influence on the actual device. In the general case, the CD-SEM can measure the bias between the target and device on the same layer after etch inspection (AEI) for all layers, the OVL between layers at AEI for most cases and after develop inspection for limited cases such as double-patterning layers. The results have shown that for the innovative process compatible hybrid targets the bias between the target and device is small, within the order of CD-SEM noise. Direct OVL measurements by CD-SEM show excellent correlation between CD-SEM and optical OVL measurements at certain conditions. This correlation helps verify the accuracy of the optical measurement results and is applicable for the imaging base OVL method using several target types advance imaging metrology, advance imaging metrology in die OVL, and the scatterometrybase OVL method. Future plans include broadening the hybrid target design to better mimic each layer process conditions such as pattern density. Additionally, for memory devices we are developing hybrid targets which enable other methods of accuracy verification.

DCM: device correlated metrology for overlay measurements

One of the main issues with overlay error metrology accuracy is the bias between results based on overlay (OVL) targets and actual device overlay error. In this study, we introduce the concept of Device Correlated Metrology (DCM), which is a systematic approach to quantifying and overcoming the bias between target-based overlay results and device overlay issues. For systematically quantifying the bias components between target and device, we introduce a new hybrid target integrating an optical OVL target with a device mimicking CD-SEM (Critical Dimension – Scanning Electron Microscope) target. The hybrid OVL target is designed to accurately represent the process influence found on the real device. In the general case, the CD-SEM can measure the bias between target and device on the same layer at AEI (After Etch Inspection) for all layers, the OVL between layers at AEI for most cases and at ADI (After Develop Inspection) for limited cases such as DPL (Double Patterning Lithography). The results shown demonstrate that for the new process compatible hybrid targets the bias between target and device is small, of the order of CD-SEM measurement uncertainty. Direct OVL measurements by CD-SEM show excellent correlation with optical OVL measurements in certain conditions. This correlation helps verify the accuracy of the optical measurement results and is applicable for imaging based OVL metrology methods using AIM or AIMid OVL targets, and scatterometry-based overlay methods such as SCOL (Scatterometry OVL). Future plans include broadening the hybrid target design to better mimic each layer’s process conditions such as pattern density. We are also designing hybrid targets for memory devices.

Non-topcoat resist design for immersion process at 32-nm node

At the 32nm node, the most important issue for mass production in immersion lithography is defectivity control. Many methods have been studied to reduce post-exposure immersion defects. Although a topcoat process demonstrates good immersion defect prevention, a topcoat-less resist process is an attractive candidate for immersion lithography due to cost reduction from a simplified process. In this paper we took the innovative approach of chemically designing an internal self-assembling barrier material that creates a thin embedded layer which functions as a topcoat. Data will be presented on this novel self assembly concept, illustrating the control of leaching, contact angle and immersion defects. Several optimized process flows with non-topcoat resists were also studied to decrease the amount of immersion defects. This study was used to verify the capability of a topcoat-less immersion process to achieve the low-defectivity levels required for 32nm node production.

Innovative fast technique for overlay accuracy estimation using archer self calibration (ASC)

As overlay margins shrink for advanced process nodes, a key overlay metrology challenge is finding the measurement conditions which optimize the yield for every device and layer. Ideally, this setup should be found in-line during the lithography measurements step. Moreover, the overlay measurement must have excellent correlation to the device electrical behavior. This requirement makes the measurement conditions selection even more challenging since it requires information about the response of both the metrology target and device to different process variations. In this work a comprehensive solution for overlay metrology accuracy, used by UMC, is described. This solution ranks the different measurement setups by their accuracy, using Qmerit, as reported by the Archer 500. This ranking was verified to match device overlay using electrical tests. Moreover, the use of Archer Self Calibration (ASC) allows further improvement of overlay measurement accuracy.

Multi-level overlay techniques for improving DPL overlay control

Overlay continues to be one of the key challenges for lithography in semiconductor manufacturing, especially in light of the accelerated pace of device node shrinks. This reality will be especially evident at 20nm node where DPL and multi-layer overlay will require 4nm or less in overlay control across many critical layers in order to meet device yield entitlements. The motivation for this paper is based on improving DPL overlay control in face of the high complexity involved with multi-layer overlay requirements. For example, the DPL-2nd-litho layer will need to achieve tight registration with the DPL-1st-litho layer, and at the same time, it will need to achieve tight overlay to the reference-litho layer, which in some cases can also be a DPL layer. Of course, multi-level overlay measurements are not new, but the combination of increased complexity of multi-DPL layers and extremely challenging overlay specifications for 20nm node together will necessitate a better understanding of multi-level overlay control, specifically in terms of root cause analysis of multi-layer related overlay errors and appropriate techniques for improvement In this paper, we start with the identification of specific overlay errors caused by multi-layer DPL processing on full film stack product wafers. After validation of these findings with inter-lot and intra-lot controlled experiments, we investigate different advanced control techniques to determine how to optimize overlay control and minimize both intra-lot and inter-lot sources of error. A new approach to overlay data analysis will also be introduced that combines empirical data with target image quality data to more accurately determine and better explain the root cause error mechanism as well as provide effective strategies for improved overlay control.

Scatterometry measurement for gate ADI and AEI critical dimension of 28-nm metal gate technology

This paper discusses the scatterometry-based metrology measurement of 28nm high k metal gate after-develop inspection (ADI) and after-etch inspection (AEI) layer structures. For these structures, the critical measurement parameters include side wall angle (SWA) and critical dimension (CD). For production process control of these structures, a metrology tool must utilize a non-destructive measurement technique, and have high sensitivity, precision and throughput. Spectroscopic critical dimension (SCD) metrology tools have been implemented in production for process control of traditional poly gate structures. For todays complex metal gate devices, extended SCD technologies are required. KLA-Tencors new SpectraShape 8810 uses multi-azimuth angles and multi-channel optics to produce the high sensitivity and precision required for measurement of critical parameters on metal gate structures. Data from process of record (POR), focus-exposure matrix (FEM) and design of experiment (DOE) wafers are presented showing the performance of this new SCD tool on metal gate ADI and AEI process structures. Metal gate AEI scatterometry measurement results are also compared to transmission electron microscopy (TEM) reference measurements. These data suggest that the SpectraShape 8810 has the required sensitivity and precision to serve as a production process monitor for 28nm and beyond complex metal gate structures.

Scatterometry or imaging overlay: a comparative study

Most fabrication facilities today use imaging overlay measurement methods, as it has been the industry’s reliable workhorse for decades. In the last few years, third-generation Scatterometry Overlay (SCOL™) or Diffraction Based Overlay (DBO-1) technology was developed, along another DBO technology (DBO-2). This development led to the question of where the DBO technology should be implemented for overlay measurements. Scatterometry has been adopted for high volume production in only few cases, always with imaging as a backup, but scatterometry overlay is considered by many as the technology of the future. In this paper we compare imaging overlay and DBO technologies by means of measurements and simulations. We outline issues and sensitivities for both technologies, providing guidelines for the best implementation of each. For several of the presented cases, data from two different DBO technologies are compared as well, the first with Pupil data access (DBO-1) and the other without pupil data access (DBO-2). Key indicators of overlay measurement quality include: layer coverage, accuracy, TMU, process robustness and robustness to process changes. Measurement data from real cases across the industry are compared and the conclusions are also backed by simulations. Accuracy is benchmarked with reference OVL, and self-consistency, showing good results for Imaging and DBO-1 technology. Process sensitivity and metrology robustness are mostly simulated with MTD (Metrology Target Designer) comparing the same process variations for both technologies. The experimental data presented in this study was done on ten advanced node layers and three production node layers, for all phases of the IC fabrication process (FEOL, MEOL and BEOL). The metrology tool used for most of the study is KLA-Tencor’s Archer 500LCM system (scatterometry-based and imaging-based measurement technologies on the same tool) another type of tool is used for DBO-2 measurements. Finally, we conclude that both imaging overlay technology and DBO-1 technology are fully successful and have a valid roadmap for the next few design nodes, with some use cases better suited for one or the other measurement technologies. Having both imaging and DBO technology options available in parallel, allows Overlay Engineers a mix and match overlay measurement strategy, providing back up when encountering difficulties with one of the technologies and benefiting from the best of both technologies for every use case.

Development of Si-HM for NTD process

Negative Tone Development (NTD) process with ArF immersion has been developed for the next generation lithography technology because it shows good resolution performance and process window for C/H and trench patterning. Because of the etch requirement, tri-layer process has been used popularly. However, most of the Si-HM materials are optimized for positive tone development process and most of them show poor lithography performance in NTD process. In this paper, we study the behaviors of Si-HM for NTD process, develop new concepts and optimize the formulation of Si-HM to match the resist for NTD process bellow N28 node device.

Reflection control for immersion lithography at 45/32-nm nodes

A new dual bottom antireflectant consisting of an organic antireflectant and a SixOyNz:H (SiON) layer has been designed for metal layers to cover both 45nm and 32nm node logic devices. Simulations have been used to optimize the optical constants of the organic antireflectant. The new antireflectant system has been evaluated on a 1.2NA tool for metal layers. The same organic antireflectant has been successfully applied to via layers at a different thickness. The overall patterning performance including profiles, line width roughness (LWR), overlap depth of focus margin (ODOF) and critical dimension (CD) uniformity before and after etch has been evaluated. The new antireflectant system meets all the patterning requirements for a manufacturable process. An immersion tool at 1.2NA was used to perform lithography tests. Simulation was performed by using ProlithTM software.

UDOF direct improvement by modulating mask absorber thickness

As the process generation migrate to advanced and smaller dimension or pitch, the mask and resist 3D effects will impact the lithography focus common window severely because of both individual depth-of-focus (iDOF) range decrease and center mismatch. Furthermore, some chemical or thermal factors, such as PEB (Post Exposure Bake) also worsen the usable depth-of-focus (uDOF) performance. So the mismatch of thru-pitch iDOF center should be considered as a lithography process integration issue, and more complicated to partition the 3D effects induced by optical or chemical factors. In order to reduce the impact of 3D effects induced by both optical and chemical issues, and improve iDOF center mismatch, we would like to propose a mask absorber thickness offset approach, which is directly to compensate the iDOF center bias by adjusting mask absorber thickness, for iso, semi-iso or dense characteristics in line, space or via patterns to enlarge common process window, i.e uDOF, which intends to provide similar application as Flexwave[1] (ASML trademark). By the way, since mask absorber thickness offset approach is similar to focus tuning or change on wafer lithography process, it could be acted as the process tuning method of photoresist (PR) profile optimization locally, PR scum improvement in specific patterns or to modulate etching bias to meet process integration request. For mass production consideration, and available material, current att-PSM blank, quartz, MoSi with chrome layer as hard-mask in reticle process, will be implemented in this experiment, i.e. chrome will be kept remaining above partial thru-pitch patterns, and act as the absorber thickness bias in different patterns. And then, from the best focus offset of thru-pitch patterns, the iDOF center shifts could be directly corrected and to enlarge uDOF by increasing the overlap of iDOF. Finally, some negative tone development (NTD) result in line patterns will be demonstrated as well.