Chung J. Kuo

Adaptive interpolation technique for scanning rate conversion

An adaptive technique for scanning rate conversion and interpolation is proposed. This technique performs better than the edge-based line average algorithm, especially for an image with more horizontal edges. Moreover, it is easy to implement and a simple VLSI architecture is proposed. Computer simulation shows that a 37.0 dB image can be obtained via our proposed technique, while edge-based line average algorithm only achieves 35.2 dB.

Adaptive postprocessor for block encoded images

Blocking effects are a major degradation in block based image coding techniques. In this paper, we propose an adaptive postprocessor for the removal of blocking effects. The adaptation is achieved by changing filter coefficients according to the local characteristics of images and the blocking effects. Here, a space-variant lowpass filter is used to smooth the pixels at block boundaries where the blocking effects are highly visible. In addition, the pixels that are closed to an edge are adaptively regional or directional lowpass filtered if the blocking effects are obvious. As for the pixels at edges, they are left untouched by the postprocessor. Therefore, blocking effects can be removed without blurring the edge sharpness. Performance improvements compared with other techniques are obtained according to simulation results. The proposed postprocessor has 0-1 dB gain (depending on the images) compared with the loop filter of H.261, the linear filter, and the nonlinear space-variant postprocessor. >

A 5.25-GHz CMOS folded-cascode even-harmonic mixer for low-voltage applications

This paper presents a 5.25-GHz folded-cascode even-harmonic mixer (FEHM) for low-voltage applications. This FEHM employs the folded technique to reduce the headroom voltage, a current reuse circuit in the RF stage to improve its linearity, and the frequency-doubling technique in the local oscillator (LO) stage to produce an LO double-frequency signal. In addition, the proposed technique exhibits the advantage of high conversion gain. In order to demonstrate the benefits and optimize the circuit design, the theoretical studies of conversion gain, linearity, and noise performance are described. For measurement, the proposed FEHM possesses conversion gain of 8.3 dB, third-order input intercept point (IIP/sub 3/) of 0.03 dBm, and second-order input intercept point (IIP/sub 2/) of 31.2 dBm under the supply voltage of 0.9 V and LO power of 5.5 dBm. The power consumption of the proposed mixer is about 4.95 mW at an IF frequency of 500 kHz.

Iteration-free fractal image coding based on efficient domain pool design

The domain pool design is one of the dominant issues which affect the coding performance of fractal image compression. In this paper, we employ the LBG algorithm and propose a block averaging method to design the efficient domain pools based on a proposed iteration-free fractal image codec. The redundancies between the generated domain blocks are reduced by the proposed methods. Therefore, we can obtain the domain pools that are more efficient than those in the conventional fractal coding schemes and thus the coding performance is improved. On the other hand, the iteration process in the conventional fractal coding scheme not only requires a large size of memory and a high computation complexity but also prolongs the decoding process. The proposed iteration-free fractal codec can overcome the problems above. In computer simulation, both the LBG-based and block-averaging methods for the domain pool design in the proposed iteration free scheme achieve excellent performances. For example, based on the proposed block-averaging method, the decoded Lena image has at least a 0.5 dB higher PSNR (under the same bit rate) and an eight-time faster decoding speed than the conventional fractal coding schemes that require iterations.

Analysis and implementation of a CMOS even harmonic mixer with current reuse for heterodyne/direct conversion receivers

This paper presents a novel topology for the even harmonic mixer (EHM). The proposed mixer employs a current reuse circuit in the RF input stage to improve its linearity, and uses the double frequency technique in the LO input stage to overcome the leakage and dc offset problems for heterodyne and direct conversion receivers, respectively. In addition, the proposed topology also has the advantages of low power consumption and high conversion gain. In order to demonstrate the benefits of the proposed mixer, theoretical analyses of linearity, conversion gain, and noise performance have been described in detail. The measured results reveal that the proposed mixer has a single-end conversion gain of 9.17 dB, third-order input intercept point (IIP/sub 3/) of -5.01 dBm, and IIP/sub 3//dc of -6.31 dB, under the supply voltage of 1.8 V, power consumption of 1.35 mW, and LO power of 5 dBm at 900 MHz.

An improved scheme for fractal image coding

The performance of the fractal image coding system is improved in our research. Comparing with our previous work and the original work accomplished by Jacquin, both the PSNR and the compression ratio are increased. Based on the local similarity of nature images, the search region of the domain blocks is confined within the neighborhood of the range block. The search region for child domain blocks are extended to get a better match process. On the other hand, testing all the possible 8 values of the contrast scaling and selecting the best one further improves the performance. The blocking effect due to the mean-coded range block is also reduced by using a post-processing technique. Here we achieve a 33.9 dB PSNR at the bit rate 0.45 bit/pixel, while our previous work and Jacquins scheme achieved 32.6 dB at 0.52 bit/pixel and 32 dB PSNR at 0.6 bit/pixel, respectively.

Image segmentation with improved watershed algorithm and its FPGA implementation

This paper is concerned with image segmentation based on watershed transform techniques. It introduces a fast, improved watershed algorithm which processes 3/spl times/3 pixels in one process. Simulation results show that the improved watershed algorithm has a better throughput and yields comparable results to those of Vincents immersion watershed algorithm. The improved algorithm is modified and formulated such that it is amenable to computing architecture implementation. An FPGA-based architecture that is developed to implement the proposed algorithm is presented. This architecture improves the applicability of this algorithm in real time applications. A description of the improved watershed algorithm, its extension to N/spl times/N pixels, and the architecture implementation is presented.

Synthesizing lateral face from frontal facial image using anthropometric estimation

We propose a method to synthesize a lateral face from a 2D gray-level image of a frontal face that provides only plane geometry but not the depth information for a 3D facial model. To estimate the depth information from the frontal face, we investigate the relationship between the frontal and lateral facial anthropometric parameters. According to anthropometric definitions on the head and face, we set up a database consisting of facial parameters measured from 70 Chinese male adults. The database serves as prior knowledge for the minimum mean square error estimation on lateral facial parameters. For each person, with his frontal facial image, we can construct his 3D facial model based on the measured frontal facial parameters and the estimated lateral parameters. Therefore, images of a lateral face can be synthesized by texture mapping from the frontal facial image.

Modified odd-even merge-sort network for arbitrary number of inputs

Modified network architecture for sorting data of any size is presented in this paper. The proposed VLSI archi- tecture is directly modified from the Batchers odd-even merge-sort network. The major advantage of the proposed architecture is its modular approach, simple and regular interconnection and easy implementation by VLSI technol- ogy.

Polynomial search algorithms for motion estimation

This paper proposes a polynomial search algorithm and architecture to solve the motion estimation problem in video coding. Simulation results show that the proposed method not only is flexible but also requires fewer computations and achieves a similar mean absolute error result compared with the existing fast search algorithms. Lastly, a VLSI architecture is also developed to efficiently implement the polynomial search algorithm.