Shuenn-Yuh Lee

An implantable wireless bidirectional communication microstimulator for neuromuscular stimulation

This paper presents the integrated circuit design for a wireless bidirectional transmission microstimulator. This implantable device is composed of an internal radio-frequency (RF) front-end circuit, a control circuit, a stimulator, and an on-chip transmitter. A 2-MHz amplitude-shift keying modulated signal, including the power and data necessary for the implantable device, is received, and a stable 3-V dc voltage and digital data will be extracted to further execute neuromuscular stimulation. The current-mode microstimulator can produce a bidirectional output current with 8-bit resolution for stimulation. The maximum stimulation current is 1 mA while the stimulation frequency is from 20 Hz to 2 kHz and the pulsewidth of stimulation current is from 150 to 500 /spl mu/s. Furthermore, the system can acquire the biological sensing signal by means of an on-chip transmitter. Most of the signal processing circuits have been designed with low-power schemes to reduce the power consumption, and the performance is also conformed to the requirements of the microstimulator. All of the circuits except for the RF link are combined in a single chip and implemented in TSMC 0.35-/spl mu/m 2P4M standard CMOS process.

Systematic Design and Modeling of a OTA-C Filter for Portable ECG Detection

This study presents a systematic design of the fully differential operational transconductance amplifier-C (OTA-C) filter for a heart activities detection apparatus. Since the linearity and noise of the filter is dependent on the building cell, a precise behavioral model for the real OTA circuit is created. To reduce the influence of coefficient sensitivity and maintain an undistorted biosignal, a fifth-order ladder-type lowpass Butterworth is employed. Based on this topology, a chip fabricated in a 0.18- mum CMOS process is simulated and measured to validate the system estimation. Since the battery life and the integration with the low-voltage digital processor are the most critical requirement for the portable diagnosis device, the OTA-based circuit is operated in the subthreshold region to save power under the supply voltage of 1V. Measurement results show that this low-voltage and low-power filter possesses the HD3 of -48.9 dB, dynamic range (DR) of 50 dB, and power consumption of 453 nW. Therefore, the OTA-C filter can be adopted to eliminate the out-of-band interference of the electrocardiogram (ECG) whose signal bandwidth is located within 250 Hz.This study presents a systematic design of the fully differential operational transconductance amplifier-C (OTA-C) filter for a heart activities detection apparatus. Since the linearity and noise of the filter is dependent on the building cell, a precise behavioral model for the real OTA circuit is created. To reduce the influence of coefficient sensitivity and maintain an undistorted biosignal, a fifth-order ladder-type lowpass Butterworth is employed. Based on this topology, a chip fabricated in a 0.18- mum CMOS process is simulated and measured to validate the system estimation. Since the battery life and the integration with the low-voltage digital processor are the most critical requirement for the portable diagnosis device, the OTA-based circuit is operated in the subthreshold region to save power under the supply voltage of 1V. Measurement results show that this low-voltage and low-power filter possesses the HD3 of -48.9 dB, dynamic range (DR) of 50 dB, and power consumption of 453 nW. Therefore, the OTA-C filter can be adopted to eliminate the out-of-band interference of the electrocardiogram (ECG) whose signal bandwidth is located within 250 Hz.

A Low-Power RFID Integrated Circuits for Intelligent Healthcare Systems

This paper presents low-power radio-frequency identification (RFID) technology for intelligent healthcare systems. With attention to power-efficient communication in the body sensor network, RF power transfer was estimated and the required low-power ICs, which are important in the development of a healthcare system with miniaturization and system integration, are discussed based on the RFID platform. To analyze the power transformation, this paper adopts a 915-MHz industrial, scientific, and medical RF with a radiation power of 70 mW to estimate the power loss under the 1-m communication distance between an RFID reader (bioinformation node) and a transponder (biosignal acquisition nodes). The low-power ICs of the transponder will be implemented in the TSMC 0.18-μm CMOS process. The simulation result reveals that the transponders IC can fit in with the link budget of the UHF RFID system.

Low-Power Analog Integrated Circuits for Wireless ECG Acquisition Systems

This paper presents low-power analog ICs for wireless ECG acquisition systems. Considering the power-efficient communication in the body sensor network, the required low-power analog ICs are developed for a healthcare system through miniaturization and system integration. To acquire the ECG signal, a low-power analog front-end system, including an ECG signal acquisition board, an on-chip low-pass filter, and an on-chip successive-approximation analog-to-digital converter for portable ECG detection devices is presented. A quadrature CMOS voltage-controlled oscillator and a 2.4 GHz direct-conversion transmitter with a power amplifier and upconversion mixer are also developed to transmit the ECG signal through wireless communication. In the receiver, a 2.4 GHz fully integrated CMOS RF front end with a low-noise amplifier, differential power splitter, and quadrature mixer based on current-reused folded architecture is proposed. The circuits have been implemented to meet the specifications of the IEEE 802.15.4 2.4 GHz standard. The low-power ICs of the wireless ECG acquisition systems have been fabricated using a 0.18 μm Taiwan Semiconductor Manufacturing Company (TSMC) CMOS standard process. The measured results on the human body reveal that ECG signals can be acquired effectively by the proposed low-power analog front-end ICs.

A 5.25-GHz CMOS folded-cascode even-harmonic mixer for low-voltage applications

This paper presents a 5.25-GHz folded-cascode even-harmonic mixer (FEHM) for low-voltage applications. This FEHM employs the folded technique to reduce the headroom voltage, a current reuse circuit in the RF stage to improve its linearity, and the frequency-doubling technique in the local oscillator (LO) stage to produce an LO double-frequency signal. In addition, the proposed technique exhibits the advantage of high conversion gain. In order to demonstrate the benefits and optimize the circuit design, the theoretical studies of conversion gain, linearity, and noise performance are described. For measurement, the proposed FEHM possesses conversion gain of 8.3 dB, third-order input intercept point (IIP/sub 3/) of 0.03 dBm, and second-order input intercept point (IIP/sub 2/) of 31.2 dBm under the supply voltage of 0.9 V and LO power of 5.5 dBm. The power consumption of the proposed mixer is about 4.95 mW at an IF frequency of 500 kHz.

A Programmable Implantable Microstimulator SoC With Wireless Telemetry: Application in Closed-Loop Endocardial Stimulation for Cardiac Pacemaker

A low-power, wireless, and implantable microstimulator system on chip with smart powering management, immediate neural signal acquisition, and wireless rechargeable system is proposed. A system controller with parity checking handles the adjustable stimulus parameters for the stimulated objective. In the current paper, the rats intra-cardiac electrogram is employed as the stimulated model in the animal study, and it is sensed by a low-voltage and low-power monitoring analog front end. The power management unit, which includes a rectifier, battery charging and detection, and a regulator, is used for the power control of the internal circuits. The stimulation data and required clock are extracted by a phase-locked-loop-based phase shift keying demodulator from an inductive AC signal. The full chip, which consumes 48 μW only, is fabricated in a TSMC 0.35 μm 2P4M standard CMOS process to perform the monitoring and pacing functions with inductively powered communication in the in vivo study.

Developing a Wireless Implantable Body Sensor Network in MICS Band

Through an integration of wireless communication and sensing technologies, the concept of a body sensor network (BSN) was initially proposed in the early decade with the aim to provide an essential technology for wearable, ambulatory, and pervasive health monitoring for elderly people and chronic patients. It has become a hot research area due to big opportunities as well as great challenges it presents. Though the idea of an implantable BSN was proposed in parallel with the on-body sensor network, the development in this area is relatively slow due to the complexity of human body, safety concerns, and some technological bottlenecks such as the design of ultralow-power implantable RF transceiver. This paper describes a new wireless implantable BSN that operates in medical implant communication service (MICS) frequency band. This system innovatively incorporates both sensing and actuation nodes to form a closed-control loop for physiological monitoring and drug delivery for critically ill patients. The sensing node, which is designed using system-on-chip technologies, takes advantage of the newly available ultralow-power Zarlink MICS transceiver for wireless data transmission. Finally, the specific absorption rate distribution of the proposed system was simulated to determine the in vivo electromagnetic field absorption and the power safety limits.

A Low-Power Bidirectional Telemetry Device With a Near-Field Charging Feature for a Cardiac Microstimulator

In this paper, wireless telemetry using the near-field coupling technique with round-wire coils for an implanted cardiac microstimulator is presented. The proposed system possesses an external powering amplifier and an internal bidirectional microstimulator. The energy of the microstimulator is provided by a rectifier that can efficiently charge a rechargeable device. A fully integrated regulator and a charge pump circuit are included to generate a stable, low-voltage, and high-potential supply voltage, respectively. A miniature digital processor includes a phase-shift-keying (PSK) demodulator to decode the transmission data and a self-protective system controller to operate the entire system. To acquire the cardiac signal, a low-voltage and low-power monitoring analog front end (MAFE) performs immediate threshold detection and data conversion. In addition, the pacing circuit, which consists of a pulse generator (PG) and its digital-to-analog (D/A) controller, is responsible for stimulating heart tissue. The chip was fabricated by Taiwan Semiconductor Manufacturing Company (TSMC) with 0.35-μm complementary metal-oxide semiconductor technology to perform the monitoring and pacing functions with inductively powered communication. Using a model with lead and heart tissue on measurement, a -5-V pulse at a stimulating frequency of 60 beats per minute (bpm) is delivered while only consuming 31.5 μW of power.In this paper, wireless telemetry using the near-field coupling technique with round-wire coils for an implanted cardiac microstimulator is presented. The proposed system possesses an external powering amplifier and an internal bidirectional microstimulator. The energy of the microstimulator is provided by a rectifier that can efficiently charge a rechargeable device. A fully integrated regulator and a charge pump circuit are included to generate a stable, low-voltage, and high-potential supply voltage, respectively. A miniature digital processor includes a phase-shift-keying (PSK) demodulator to decode the transmission data and a self-protective system controller to operate the entire system. To acquire the cardiac signal, a low-voltage and low-power monitoring analog front end (MAFE) performs immediate threshold detection and data conversion. In addition, the pacing circuit, which consists of a pulse generator (PG) and its digital-to-analog (D/A) controller, is responsible for stimulating heart tissue. The chip was fabricated by Taiwan Semiconductor Manufacturing Company (TSMC) with 0.35-μm complementary metal-oxide semiconductor technology to perform the monitoring and pacing functions with inductively powered communication. Using a model with lead and heart tissue on measurement, a -5-V pulse at a stimulating frequency of 60 beats per minute (bpm) is delivered while only consuming 31.5 μW of power.

Analysis and Implementation of a 0.9-V Voltage-Controlled Oscillator With Low Phase Noise and Low Power Dissipation

A voltage-controlled oscillator (VCO) with low phase noise and low power dissipation for IEEE 802.11b is proposed. A negative resistance multiple-gated circuit with a bypass capacitor is adopted to improve phase noise. The chip is implemented in 0.18-mum CMOS process under a supply voltage of 0.9 V and power consumption of 2.7 mW. Its measured results show that the VCO has a phase noise of -122.3 dBc/Hz at 1-MHz offset frequency from the carrier frequency, and the tuning frequency from 2.17 to 2.73 GHz can be obtained under the tuning voltage of -0.9 to 0.9 V. The theoretical analysis and design consideration are also conducted in detail to show the benefits of the proposed VCO.

A Low-Voltage and Low-Power Adaptive Switched-Current Sigma–Delta ADC for Bio-Acquisition Microsystems

An ultralow-voltage and low-power adaptive sigma-delta analog-to-digital converter (SDADC) with a 10-bit dynamic range for bio-microsystem applications is presented. The proposed SDADC includes a switched-current sigma-delta modulator (SISDM) and a digital decimator. In order to achieve the low-voltage requirement, a novel class-AB switched-current memory cell is adopted to implement the SISDM with the oversampling ratio (OSR) of 64. In addition, a proposed differential current comparator and a low-voltage 1-bit switched-current digit-to-analog converter (SIDAC) are used for the design of the SDM. Benefits from the SISDM using the class-AB memory cell are low power consumption and high dynamic range. Moreover, a new single-multiplier structure is presented to implement the finite-impulse-response (FIR) digital filters which are the major hardware elements in the decimator. For the various applications with different biosignal frequencies, the SDADC could be manipulated in different operating modes. The overall ADC has been implemented in a TSMC 0.18-mum 1P6M standard CMOS process technology. Without a voltage booster to raise the gate voltage of switches, measurement results show that the SISDM has a dynamic range over 60 dB and a power consumption of 180 muW with an input signal of 1.25-kHz sinusoid wave and 5-kHz bandwidth under a single 0.8-V power supply for electroneurography signals. In addition, the postlayout simulations of SDADC including SISDM and decimator reveal that the dynamic range is still over 60 dB without degrading by digital circuits