Chung Len Lee

An improved fast acquisition PFD with zero blind zone for the PLL application

An improved fast acquisition phase-frequency detector (PFD) for Phase-Locked Loop (PLL) is presented. The proposed PFD completely eliminates the blind zone, which is caused by the missing input edge during reset pulse. It has a linear output range and a saturated output when the phase error is in [0, π] and [π, 2π]. The simulation results with the SMIC 65nm CMOS technology file show that, comparing with the published works, the proposed nonlinear gain PFD has a faster lock process, and improves the maximum operating frequency to as higher as 1GHz.

A new programmable delay cell with good symmetry for the digital IR-UWB pulse generator

This paper proposes a new programmable delay cell controlled by a 4-bit binary coding inverter array for the digital impulse radio (IR) ultra wide band (UWB) pulse generator. Implemented in a TSMC 0.18μm technology, simulation results show that the proposed circuit can generate a coarse tuning range of pulse width with good symmetry from 118ps to 227ps with different control signal from 0001 to 1111. The UBW pulse generator consumes only 1.6mW at 1Gbit/s data rate when the control signal is 0001 at a VDD voltage of 1.8V and occupies a small area of 162μm*44μm.

A 1.8ppm/°C Low Temperature Coefficient Curvature Compensated Bandgap for the Low Voltage Application

A new CMOS curvature compensated bandgap reference circuit which uses two different types of material to realize its resistors in an improved structure is presented. Implemented in a 0.18 μm technology, it achieves performance of a temperature coefficient of 1.8 ppm/°C over 0 ~ 100°C, a line regulation of 0.017%/V over the range 1.2 ~3 V and a power supply rejection ratio of 82 dB@1 Hz. It can offer a reference voltage of 1.1 V but occupy an area of only 0.049 mm2.

A 100MHz PGA with DC offset cancellation for UWB receiver

In this paper, a Programmable Gain Amplifier (PGA) used for OOK UWB receiver is presented. It achieves a 100MHz bandwidth and a 19-40dB 8-step programmable gain. Furthermore, voltage-current DC feedback technique is adopted in order to realize DC offset cancellation (DCOC) at the output. This work is implemented in TSMC 0.18um CMOS process and consumes 1.26mW power.

A 2.34–3.29GHz CMOS LC VCO with low phase noise and low power

A low phase noise wideband LC VCO is designed and presented. In this VCO, a symmetrical LC tank with proper arrangement of varactors is used to extend its tuning range. Results from the post layout simulation show that the VCO achieved a wide tuning range from 2.34GHz to 3.29GHz. Moreover, a noise cancellation technique is adopted to achieve better phase noise performance. The VCO exhibits that phase noise is lower than -120.1dBc/Hz at 1-MHz offset frequency. The circuit consumes 2.38mA of power from a 1.8V supply.

A UWB mixer with a balanced wide band active balun using crossing centertaped inductor

A high gain 3-5GHz mixer merged with a very balanced wideband active balun is presented and demonstrated. It uses a Gilbert type folded structure with the active balun as the input trans-conductance stage and with a PMOS switch stage. The implemented circuit in the 0.18um CMOS technology exhibits less than 1dB amplitude imbalance in 2.06-5.2GHz, less than 1.5dB in 0.55-5.7GHz and less than 2 degree phase imbalance through 1.37GHz to 5.07GHz. The mixer exhibits a high IIP3 of -3dBm and a high isolation of LO-RF about -100dB in the wide bandwidth. It consumes only 6.2mW under a 1.8V power supply.

Self-heating burn-in pattern generation based on the genetic algorithm incorporated with a BACK-like procedure

In integrated circuit (IC) burn-in, it is desirable to produce efficient input patterns to assist heating for circuit under test. This study proposes and demonstrates an approach which uses the genetic algorithm incorporating with a BACK-like procedure to generate the patterns which produce the maximal and/or uniform node transition as well as power dissipation for burn-in application. A multi-step strategy is applied in the algorithm, and a transition measure is defined to guide the backtracing of the BACK-like procedure, improving the efficiency in searching the target patterns. Experimental results show that the approach generates better pattern pairs which produce either the maximal transition count or the maximal power dissipation than that of all the other published results. It is also able to generate the pattern sequence which achieves more uniformly stressing, by 30% improvement statistically, for each gate of the circuit under test. The computation time, because of using a divide-and-conquer strategy in this approach, is also reasonable, making it useful in the practical IC burn-in application.

Impulse Radio Demodulation Scheme for Impulse Radio UWB Receiver

A new demodulation scheme for BPSK modulated first order derivative Gaussian pulses is proposed. The scheme first transfers the BPSK modulated data into the corresponding PWM modulated data, and filters out the narrower pulses to differentiate “0” and “1” state. The key idea of this method is based on detecting the modulated data pulse width. According to analysis of relevant paper, this method will fit the near field inductive coupling system for use like chip to chip wireless communication or centimeter range multimedia communications application. The simulation result shows that this demodulation method works well and supports hundreds of Megabits data rate (500 Mbps).

A high gain, wide band (2–10 GHz), and low noise active balun merged folded mixer for the full-band UWB application

A high gain, wide band (2-10GHz) but low noise mixer is presented and demonstrated. It uses a Gilbert type folded structure with an active balun as the input trans-conductance stage and a PMOS switch stage. Because of the structure, each stage can be separately set its bias current to achieve high gain and low noise. The implemented circuit in the 0.18 um CMOS technology exhibits a high conversion gain (CG), 17.6 dB at 4 GHz and 8.1 dB at 10 GHz, a SSB noise figure (NF) of 15.6 dB, an IIP3 of -3.4 dBm to +2 dBm, and an isolation of RF-LO of -144 dB. The mixer power consumption is about 7.8 mW under a 1.8 V power supply.

An improved X-filling strategy based on the Multilayer Data Copy scheme for test data and power reduction for SoC

Multilayer Data Copy (MDC) [1] is an effective test data compression scheme for achieving low shift-in power for the multiple scan chain of SoC. This work improves the scheme by employing a B-filling strategy to fill X (dont care) bits to further reduce the test data volume and the test power. Experimental results show that it can achieve more 3% of the test data volume reduction and more than two times of power savings on benchmark circuits.