Xiaole Cui

Potentiating effect of spinosin, a C-glycoside flavonoid of Semen Ziziphi spinosae, on pentobarbital-induced sleep may be related to postsynaptic 5-HT1A receptors

Previous results have suggested that spinosin, a C-glycoside flavonoid of Semen Ziziphi spinosae, potentiates pentobarbital-induced sleep via the serotonergic system. The present study investigated whether spinosin potentiates pentobarbital-induced sleep via serotonin-1A (5-hydroxytryptamine, 5-HT(1A)) receptors. The results demonstrated that spinosin significantly augmented pentobarbital (35 mg/kg, i.p.)-induced sleep in rats, reflected by reduced sleep latency and increased total sleep time, non-rapid eye movement (NREM) sleep time, and REM sleep time. With regard to NREM sleep duration, spinosin mainly increased slow-wave sleep (SWS). Additionally, spinosin (15mg/kg, i.g.) significantly antagonized 5-HT(1A) agonist 8-OH-DPAT (0.1mg/kg, i.p.)-induced reductions in total sleep time, NREM sleep, REM sleep, and SWS in pentobarbital-treated rats. These results suggest that spinosin may be an antagonist at postsynaptic 5-HT(1A) receptors because these effects of 8-OH-DPAT were considered to be mediated via postsynaptic 5-HT(1A) receptors. Moreover, co-administration of spinosin and the 5-HT(1A) antagonist 4-iodo-N-{2-[4-(methoxyphenyl)-1-piperazinyl]ethyl}-N-2-pyridinylbenzamide (p-MPPI), at doses that are ineffective when administered alone (spinosin 5mg/kg, p-MPPI 1mg/kg), had significant augmentative effects on pentobarbital-induced sleep, reflected by reduced sleep latency and increased total sleep time, NREM sleep, and REM sleep. In contrast to the attenuating effects of p-MPPI on REM sleep via presynaptic 5-HT(1A) autoreceptors, 15mg/kg spinosin significantly increased REM sleep. These results suggest that the effect of spinosin on REM sleep in pentobarbital-treated rats may be related to postsynaptic 5-HT(1A) receptors.

An Enhancement of Crosstalk Avoidance Code Based on Fibonacci Numeral System for Through Silicon Vias

Through silicon vias (TSVs) play an important role as the vertical electrical connections in 3-D stacked integrated circuits. However, the closely clustered TSVs suffer from the crosstalk noise between the neighboring TSVs, and result in the extra delay and the deterioration of signal integrity. For a

An improved fast acquisition PFD with zero blind zone for the PLL application

3 \times 3

A new programmable delay cell with good symmetry for the digital IR-UWB pulse generator

TSV array, the severity of crosstalk noise in the center victim TSV is classified into 11 levels, which is defined as 0C to 10C from low noise to high noise, depending on the combinations of the digital patterns applied to the TSV array. An enhanced code based on the Fibonacci number system (FNS) to suppress the crosstalk noise below 6C level is proposed, in which both the redundancy of numbers and the nonuniqueness of Fibonacci-based binary codeword are utilized to search the proper codeword. Experimental results show that the proposed technique decreases about 22% latency of TSVs comparing with the worst crosstalk cases. This technique is applicable in the large-scale TSV array for it has a quasi-linear hardware overhead, and its system overhead is less than that of the 3-D 4-LAT counterpart if the data width is greater than 18, and it has good usability for it consumes less power per TSV and achieves lower bit error rate at the interested frequency range comparing with that of the original FNS coding technique.

A 1.8ppm/°C Low Temperature Coefficient Curvature Compensated Bandgap for the Low Voltage Application

An improved fast acquisition phase-frequency detector (PFD) for Phase-Locked Loop (PLL) is presented. The proposed PFD completely eliminates the blind zone, which is caused by the missing input edge during reset pulse. It has a linear output range and a saturated output when the phase error is in [0, π] and [π, 2π]. The simulation results with the SMIC 65nm CMOS technology file show that, comparing with the published works, the proposed nonlinear gain PFD has a faster lock process, and improves the maximum operating frequency to as higher as 1GHz.

A test pattern selection method for dynamic burn-in of logic circuits based on ATPG technique

This paper proposes a new programmable delay cell controlled by a 4-bit binary coding inverter array for the digital impulse radio (IR) ultra wide band (UWB) pulse generator. Implemented in a TSMC 0.18μm technology, simulation results show that the proposed circuit can generate a coarse tuning range of pulse width with good symmetry from 118ps to 227ps with different control signal from 0001 to 1111. The UBW pulse generator consumes only 1.6mW at 1Gbit/s data rate when the control signal is 0001 at a VDD voltage of 1.8V and occupies a small area of 162μm*44μm.

Improving DFA attacks on AES with unknown and random faults

A new CMOS curvature compensated bandgap reference circuit which uses two different types of material to realize its resistors in an improved structure is presented. Implemented in a 0.18 μm technology, it achieves performance of a temperature coefficient of 1.8 ppm/°C over 0 ~ 100°C, a line regulation of 0.017%/V over the range 1.2 ~3 V and a power supply rejection ratio of 82 dB@1 Hz. It can offer a reference voltage of 1.1 V but occupy an area of only 0.049 mm2.

Impact of channel line-edge roughness on junctionless FinFET

State transition of nodes in the circuit generates heat which usually needs to be minimized for reliability consideration. In this work, instead, the heat generated is used to burn-in the CUT. A burn-in test pattern selection technique based on the ATPG approach for maximizing the dynamic power of the CUT is proposed. Experimental results show that the technique is effective in selecting the patterns which offer maximal power. It can be applied into the burn-in of logic circuits and SoCs in an energy saving manner.

An enhanced decoder for multiple-bit error correcting BCH codes

Differential fault analysis (DFA) aiming at the advanced encryption standard (AES) hardware implementations has become a widely research topic. Unlike theoretical model, in real attack scenarios, popular and practical fault injection methods like supply voltage variation will introduce faults with random locations, unknown values and multibyte. For analyzing this kind of faults, the previous fault model needed six pairs of correct and faulty ciphertexts to recover the secret round-key. In this paper, on the premise of accuracy, a more efficient DFA attack with unknown and random faults is proposed. We introduce the concept of theoretical candidate number in the fault analysis. Based on this concept, the correct round-key can be identified in advance, so the proposed attack method can always use the least pairs of correct and faulty ciphertexts to accomplish the DFA attacks. To further support our opinion, random fault attacks based on voltage violation were taken on an FPGA board. Experiment results showed that about 97.3% of the attacks can be completed within 3 pairs of correct and faulty ciphertexts. Moreover, on average only 2.17 pairs of correct and faulty ciphertexts were needed to find out the correct round-key, showing significant advantage of efficiency compared with previous fault models. On the other hand, less amount of computation in the analyses can be realized with a high probability with our model, which also effectively improves the time efficiency in DFA attacks with unknown and random faults.创新点在针对AES算法的随机类型故障, 传统的多字节故障模型需要分析6个故障密文才能恢复正确的四字节密钥。为了提高分析效率, 本文提出了一种针对随机类型故障的高效率差分分析算法。在保证分析准确性的前提下, 我们利用理论密钥候选值数量的概念, 设计了一种新的故障分析算法, 该算法能够根据实际的故障注入情况, 用最少的故障密文数提前恢复密钥, 并有效减小计算复杂度。针对AES算法的实际攻击结果表明, 该算法平均只需要分析2.17个故障密文即可恢复密钥, 并且97.3%的故障攻击实例都能在3组故障密文分析内完成攻击, 有效提高了分析效率。

A 2.34–3.29GHz CMOS LC VCO with low phase noise and low power

The impact of channel line-edge roughness (LER) on Junctionless FinFET device (JL-FinFET) is investigated by using the 3-D statistical simulation. Then the substantial influence of its narrowest width of the JL-FinFET is defined and presented. The results show that JL-FinFET is more sensitive to LER than inversion-mode FinFET. Further, the performance including the threshold voltage and on-state current is observed to be determined by the narrowest width of channel. The narrower channel has smaller on-state current and larger threshold voltage. The variations of on-state current caused by LER increase as the place of the narrowest channel width moving from drain to source. These imply that it is important to reduce the LER near the source side to suppress performance variations.